COP8SGE5_14 Datasheet, PDF (26/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
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The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits:
T1C3 Timer T1 mode control bit
T1C2 Timer T1 mode control bit
T1C1 Timer T1 mode control bit
T1C0 Timer T1 Start/Stop control in timer
modes 1 and 2, T1 Underflow Interrupt Pending Flag in timer mode 3
MSEL Selects G5 and G4 as MICROWIRE/PLUS signals SK and SO respectively
IEDG External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
SL1 & SL0 Select the MICROWIRE/PLUS clock divide by (00 = 2, 01 = 4, 1x = 8)
PSW Register (Address X′00EF)
HC
C
T1PNDA
Bit 7
T1ENA
EXPND
BUSY
EXEN
GIE
Bit 0
The PSW register contains the following select bits:
HC Half Carry Flag
C Carry Flag
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA in mode 1, T1 Underflow in Mode 2, T1A capture
edge in mode 3)
T1ENA Timer T1 Interrupt Enable for Timer Underflow or T1A Input capture edge
EXPND External interrupt pending
BUSY MICROWIRE/PLUS busy shifting flag
EXEN Enable external interrupt
GIE Global interrupt enable (enables interrupts)
The Half-Carry flag is also affected by all the instructions that affect the Carry flag. The SC (Set Carry) and R/C
(Reset Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and R/C
instructions, ADC, SUBC, RRC and RLC instructions affect the Carry and Half Carry flags.
ICNTRL Register (Address X′00E8)
Reserved
Bit 7
LPEN
T0PND
T0EN
µWPND
µWEN
T1PNDB
T1ENB
Bit 0
The ICNTRL register contains the following bits:
Reserved This bit is reserved and must be zero
LPEN L Port Interrupt Enable (Multi-Input Wakeup/Interrupt)
T0PND Timer T0 Interrupt pending
T0EN Timer T0 Interrupt Enable (Bit 12 toggle)
μWPND MICROWIRE/PLUS interrupt pending
μWEN Enable MICROWIRE/PLUS interrupt
T1PNDB Timer T1 Interrupt Pending Flag for T1B capture edge
T1ENB Timer T1 Interrupt Enable for T1B Input capture edge
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