COP8SGE5_14 Datasheet, PDF (30/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
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The timer value gets copied over into the register when a trigger event occurs on its corresponding pin. Control
bits, TxC3, TxC2 and TxC1, allow the trigger events to be specified either as a positive or a negative edge. The
trigger condition for each input pin can be specified independently.
The trigger conditions can also be programmed to generate interrupts. The occurrence of the specified trigger
condition on the TxA and TxB pins will be respectively latched into the pending flags, TxPNDA and TxPNDB. The
control flag TxENA allows the interrupt on TxA to be either enabled or disabled. Setting the TxENA flag enables
interrupts to be generated when the selected trigger condition occurs on the TxA pin. Similarly, the flag TxENB
controls the interrupts from the TxB pin.
Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer
TxC0 pending flag (the TxC0 control bit serves as the timer underflow interrupt pending flag in the Input Capture
mode). Consequently, the TxC0 control bit should be reset when entering the Input Capture mode. The timer
underflow interrupt is enabled with the TxENA control flag. When a TxA interrupt occurs in the Input Capture
mode, the user must check both the TxPNDA and TxC0 pending flags in order to determine whether a TxA input
capture or a timer underflow (or both) caused the interrupt.
Figure 26 shows a block diagram of the timer T1 in Input Capture mode. Timer T2 and T3 are identical to T1.
Figure 26. Timer in Input Capture Mode
TIMER CONTROL FLAGS
The control bits and their functions are summarized below.
TxC3 Timer mode control
TxC2 Timer mode control
TxC1 Timer mode control
TxC0 Timer Start/Stop control in Modes 1 and 2 (Processor Independent PWM and External Event Counter),
where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in Mode 3 (Input Capture)
TxPNDA Timer Interrupt Pending Flag
TxENA Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
TxPNDB Timer Interrupt Pending Flag
TxENB Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:
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