COP8SGE5_14 Datasheet, PDF (17/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

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COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
FUNCTIONAL DESCRIPTION
The architecture of the devices are a modified Harvard architecture. With the Harvard architecture, the program
memory ROM is separated from the data store memory (RAM). Both ROM and RAM have their own separate
addressing space with separate address buses. The architecture, though based on the Harvard architecture,
permits transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift operation in one instruction (t_C) cycle time.
There are six CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be optionally post auto incremented or decremented.
S is the 8-bit Segment Address Register used to extend the lower half of the address range (00 to 7F) into 256
data segments of 128 bytes each.
SP is the 8-bit stack pointer, which points to the subroutine/interrupt stack (in RAM). With reset the SP is
initialized to RAM address 02F Hex (devices with 64 bytes of RAM), or initialized to RAM address 06F Hex
(devices with 128 bytes of RAM).
All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter
(PC).
PROGRAM MEMORY
The program memory consists of varies sizes of ROM. These bytes may hold program instructions or constant
data (data tables for the LAID instruction, jump vectors for the JID instruction, and interrupt vectors for the VIS
instruction). The program memory is addressed by the 15-bit program counter (PC). All interrupts in the device
vector to program memory location 0FF Hex. The contents of the program memory read 00 Hex in the erased
state. Program execution starts at location 0 after RESET.
DATA MEMORY
The data memory address space includes the on-chip RAM and data registers, the I/O registers (Configuration,
Data and Pin), the control registers, the MICROWIRE/PLUS SIO shift register, and the various registers, and
counters associated with the timers (with the exception of the IDLE timer). Data memory is addressed directly by
the instruction or indirectly by the B, X and SP pointers.
The data memory consists of 256 or 512 bytes of RAM. Sixteen bytes of RAM are mapped as “registers” at
addresses 0F0 to 0FE Hex. These registers can be loaded immediately, and also decremented and tested with
the DRSZ (decrement register and skip if zero) instruction. The memory pointer registers X, SP and B are
memory mapped into this space at address locations 0FC to 0FE Hex respectively, with the other registers
(except 0FF) being available for general usage.
The instruction set permits any bit in memory to be set, reset or tested. All I/O and registers (except A and PC)
are memory mapped; therefore, I/O bits and register bits can be directly and individually set, reset and tested.
The accumulator (A) bits can also be directly and individually tested.
NOTE
RAM contents are undefined upon power-up.
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