COP8SGE5_14 Datasheet, PDF (37/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

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COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
PE: Flags a Parity Error. Read only, cleared on read, cleared on reset.
PE = 0 Indicates no Parity Error has been detected since the last time the ENUR register was read.
PE = 1 Indicates the occurrence of a Parity Error.
SPARE: Reserved for future use. Read/Write, cleared on reset.
RBIT9: Contains the ninth data bit received when the USART is operating with nine data bits per frame. Read
only, cleared on reset.
ATTN: ATTENTION Mode is enabled while this bit is set. This bit is cleared automatically on receiving a
character with data bit nine set. Read/Write, cleared on reset.
XMTG: This bit is set to indicate that the USART is transmitting. It gets reset at the end of the last frame (end of
last Stop bit). Read only, cleared on reset.
RCVG: This bit is set high whenever a framing error occurs and goes low when RDX goes high. Read only,
cleared on reset.
ENUI-USART Interrupt and Clock Source Register
(Address at 0BC)
STP2
STP78
ETDX
SSEL
XRCLK
XTCLK
ERI
Bit 7
ETI
Bit 0
STP2: This bit programs the number of Stop bits to be transmitted. Read/Write, cleared on reset.
STP2 = 0 One Stop bit transmitted.
STP2 = 1 Two Stop bits transmitted.
STP78: This bit is set to program the last Stop bit to be 7/8th of a bit in length. Read/Write, cleared on reset.
ETDX: TDX (USART Transmit Pin) is the alternate function assigned to Port L pin L2; it is selected by setting
ETDX bit. To simulate line break generation, software should reset ETDX bit and output logic zero to TDX pin
through Port L data and configuration registers. Read/Write, cleared on reset.
SSEL: USART mode select. Read/Write, cleared on reset.
SSEL = 0 Asynchronous Mode.
SSEL = 1 Synchronous Mode.
XRCLK: This bit selects the clock source for the receiver section. Read/Write, cleared on reset.
XRCLK = 0 The clock source is selected through the PSR and BAUD registers.
XRCLK = 1 Signal on CKX (L1) pin is used as the clock.
XTCLK: This bit selects the clock source for the transmitter section. Read/Write, cleared on reset.
XTCLK = 0 The clock source is selected through the PSR and BAUD registers.
XTCLK = 1 Signal on CKX (L1) pin is used as the clock.
ERI: This bit enables/disables interrupt from the receiver section. Read/Write, cleared on reset.
ERI = 0 Interrupt from the receiver is disabled.
ERI = 1 Interrupt from the receiver is enabled.
ETI: This bit enables/disables interrupt from the transmitter section. Read/Write, cleared on reset.
ETI = 0 Interrupt from the transmitter is disabled.
ETI = 1 Interrupt from the transmitter is enabled.
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