COP8SGE5_14 Datasheet, PDF (51/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

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COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
PORT L INTERRUPTS
Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored
into the same service subroutine.
The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L
to be individually enabled or disabled. The register WKEDG specifies the trigger condition to be either a positive
or a negative edge. Finally, the register WKPND latches in the pending trigger conditions.
The GIE (Global Interrupt Enable) bit enables the interrupt function.
A control flag, LPEN, functions as a global interrupt enable for Port L interrupts. Setting the LPEN flag will enable
interrupts and vice versa. A separate global pending flag is not needed since the register WKPND is adequate.
Since Port L is also used for waking the device out of the HALT or IDLE modes, the user can elect to exit the
HALT or IDLE modes either with or without the interrupt enabled. If he elects to disable the interrupt, then the
device will restart execution from the instruction immediately following the instruction that placed the
microcontroller in the HALT or IDLE modes. In the other case, the device will first execute the interrupt service
routine and then revert to normal operation. (See HALT MODE for clock option wakeup information.)
INTERRUPT SUMMARY
The device uses the following types of interrupts, listed below in order of priority:
1. The Software Trap non-maskable interrupt, triggered by the INTR (00 opcode) instruction. The Software Trap
is acknowledged immediately. This interrupt service routine can be interrupted only by another Software
Trap. The Software Trap should end with two RPND instructions followed by a restart procedure.
2. Maskable interrupts, triggered by an on-chip peripheral block or an external device connected to the device.
Under ordinary conditions, a maskable interrupt will not interrupt any other interrupt routine in progress. A
maskable interrupt routine in progress can be interrupted by the non-maskable interrupt request. A maskable
interrupt routine should end with an RETI instruction or, prior to restoring context, should return to execute
the VIS instruction. This is particularly useful when exiting long interrupt service routiness if the time between
interrupts is short. In this case the RETI instruction would only be executed when the default VIS routine is
reached.
WATCHDOG/Clock Monitor
Each device contains a user selectable WATCHDOG and clock monitor. The following section is applicable only
if WATCHDOG feature has been selected in the ECON register. The WATCHDOG is designed to detect the user
program getting stuck in infinite loops resulting in loss of program control or “runaway” programs.
The WATCHDOG logic contains two separate service windows. While the user programmable upper window
selects the WATCHDOG service time, the lower window provides protection against an infinite program loop that
contains the WATCHDOG service instruction.
The Clock Monitor is used to detect the absence of a clock or a very slow clock below a specified rate on the CKI
pin.
The WATCHDOG consists of two independent logic blocks: WD UPPER and WD LOWER. WD UPPER
establishes the upper limit on the service window and WD LOWER defines the lower limit of the service window.
Servicing the WATCHDOG consists of writing a specific value to a WATCHDOG Service Register named
WDSVR which is memory mapped in the RAM. This value is composed of three fields, consisting of a 2-bit
Window Select, a 5-bit Key Data field, and the 1-bit Clock Monitor Select field. Table 8 shows the WDSVR
register.
Table 8. WATCHDOG Service Register (WDSVR)
Window Select
Key Data
Clock Monitor
X
X
0
1
1
0
0
Y
7
6
5
4
3
2
1
0
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