COP8SGE5_14 Datasheet, PDF (56/82 Pages) Texas Instruments – COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART

COP8SGE5, COP8SGE7, COP8SGH5
COP8SGK5, COP8SGR5, COP8SGR7
SNOS516E – JANUARY 2000 – REVISED APRIL 2013
Table 12. MICROWIRE/PLUS Mode Settings⁽¹⁾ (continued)
G4 (SO)
Config. Bit
0
G5 (SK)
Config. Bit
0
G4
Fun.
TRI-
STATE
G5
Fun.
Ext.
SK
Operation
MICROWIRE/PLUS
Slave
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The user must set the BUSY flag immediately upon entering the Slave mode. This ensures that all data bits sent
by the Master is shifted properly. After eight clock pulses the BUSY flag is clear, the shift clock is stopped, and
the sequence may be repeated.
Alternate SK Phase Operation and SK Idle P
The device allows either the normal SK clock or an alternate phase SK clock to shift data in and out of the SIO
register. In both the modes the SK idle polarity can be either high or low. The polarity is selected by bit 5 of Port
G data register. In the normal mode data is shifted in on the rising edge of the SK clock and the data is shifted
out on the falling edge of the SK clock. In the alternate SK phase operation, data is shifted in on the falling edge
of the SK clock and shifted out on the rising edge of the SK clock. Bit 6 of Port G configuration register selects
the SK edge.
A control flag, SKSEL, allows either the normal SK clock or the alternate SK clock to be selected. Resetting
SKSEL causes the MICROWIRE/PLUS logic to be clocked from the normal SK signal. Setting the SKSEL flag
selects the alternate SK clock. The SKSEL is mapped into the G6 configuration bit. The SKSEL flag will power
up in the reset condition, selecting the normal SK signal.
SK Phase
Normal
Alternate
Alternate
Normal
Table 13. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase
Port G
G6 (SKSEL)
Config. Bit
0
1
0
1
G5 Data Bit
0
0
1
1
SO Clocked Out On:
SK Falling Edge
SK Rising Edge
SK Rising Edge
SK Falling Edge
SI Sampled On:
SK Rising Edge
SK Falling Edge
SK Falling Edge
SK Rising Edge
SK Idle Phase
Low
Low
High
High
Figure 38. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being Low
Figure 39. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being Low
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