DS90UH940-Q1 Datasheet, PDF (8/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
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PIN
NAME
VDD12_CSI0
VDDP12_CSI
VDD12_CSI1
VDDL12_0
VDDL12_1
VDDP12_CH0
VDDR12_CH0
VDDP12_CH1
VDDR12_CH1
CAP_PLL0
CAP_PLL1
CAP_I2S
VSS
OTHER PINS
CMLOUTP
CMLOUTN
NUMBER
20
32
33
6
44
51
52
60
57
49
64
2
DAP
62
63
I/O, TYPE
Power
CAP
Ground
O, CML
Pin Functions (continued)
DESCRIPTION
1.2V (±5%) supplies. Requires 10 µF, 1 µF, 0.1 µF, and 0.01 µF capacitors to GND at
each VDD pin.
Decoupling capacitor connection for on-chip regulator. Each requires a 0.1 µF
decoupling capacitor to GND.
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 32 vias.
Monitor point for equalized differential signal.
Layout recommendation:
1) place 0.1 µF series capacitor on CMLOUTP and CMLOUTN
2) place 100ohm termination between 0.1 µF away from CMLOUTP and CMLOUTN
pins
3) place test points from 0.1 µF capacitors
The definitions below define the functionality of the I/O cells for each pin.
I/O TYPE:
• P = Power Supply
• G = Ground
• CML = CML Interface
• DPHY = MIPI DPHY Interface
• Analog = Analog Interface
• LVCMOS = LVCMOS pin; Referenced to VDDIO IO supply
• I = Input
• O = Output
• I/O = Input/Output
• PD, PU = Internal Pull-Down/Pull-Up (All strap pins have weak internal pull-ups or pull-downs. If the default strap value is needed to be
changed then an external resistor should be used.)
• Multi-function pin
8
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