DS90UH940-Q1 Datasheet, PDF (67/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

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DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
Register Maps (continued)
Table 12. Serial Control Bus Registers (continued)
ADD
(hex)
0x83
0x84
0x90
0x91
0x92
0x93
0x94
0xC0
Register
Name
RX_BKSV3
RX_BKSV4
TX_KSV0
TX_KSV1
TX_KSV2
TX_KSV3
TX_KSV4
HDCP_DBG
Bit(s)
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7
6
Function
BKSV3
BKSV4
TX_KSV0
TX_KSV1
TX_KSV2
TX_KSV3
TX_KSV4
RESERVED
HDCP_I2C_TO_
DIS
Type
R
R
R
R
R
R
R
R
R
5:4 RESERVED
R
3
RGB_CHKSUM_ R
EN
2
FAST_LV
R
1
TMR_SPEEDUP R
0
HDCP_I2C_
R
FAST
0xC1 HDCP_DBG 7:2
2
1
RESERVED
RW
NO_DECRYPT RW
0
HDCP_EN_
RW
MODE
Default
Description
Value (hex)
0
BKSV3: Value of byte3 of the Receiver KSV.
0
BKSV4: Value of byte4 of the Receiver KSV.
0
TX_KSV0: Value of byte0 of the Transmitter KSV.
0
TX_KSV1: Value of byte1 of the Transmitter KSV.
0
TX_KSV2: Value of byte2 of the Transmitter KSV.
0
TX_KSV3: Value of byte3 of the Transmitter KSV.
0
TX_KSV4: Value of byte4 of the Transmitter KSV.
0
Reserved
0
HDCP I2C Timeout Disable:
Setting this bit to a 1 will disable the bus timeout function in the
HDCP I2C master. When enabled, the bus timeout function
allows the I2C master to assume the bus is free if no signaling
occurs for more than 1 second. Set via the HDCP_DBG register
in the HDCP Transmitter.
0
Reserved
0
Enable RGB video line checksum:
Enables sending of ones-complement checksum for each 8-bit
RGB data channel following end of each video data line. Set via
the HDCP_DBG register in the HDCP Transmitter.
0
Fast Link Verification:
HDCP periodically verifies that the HDCP Receiver is correctly
synchronized. Setting this bit will increase the rate at which
synchronization is verified. When set to a 1, Pj is computed
every 2 frames and Ri is computed every 16 frames. When set
to a 0, Pj is computed every 16 frames and Ri is computed
every 128 frames. Set via the HDCP_DBG register in the HDCP
Transmitter.
0
Timer Speedup:
Speed up HDCP authentication timers. Set via the HDCP_DBG
register in the HDCP Transmitter.
0
HDCP I2C Fast mode Enable:
Setting this bit to a 1 will enable the HDCP I2C Master in the
HDCP Receiver to operation with Fast mode timing. If set to a
0, the I2C Master will operation with Standard mode timing. Set
via the HDCP_DBG register in the HDCP Transmitter.
0
Reserved
0
No Decrypt:
When set to a 1, the HDCP Receiver will output the encrypted
data on the RGB pins. All other functions will work normally.
This provides a simple way of showing that the link is
encrypted.
0
HDCP Enable Mode:
This bit controls whether the HDCP Repeater function will
enable HDCP in attached HDCP Transmitters if it detects
HDCP is already enabled.
1 : Don't re-enable HDCP if already enabled.
0 : Re-enable HDCP at start of authentication, even if HDCP
Transmitter already has HDCP enabled.
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