DS90UH940-Q1 Datasheet, PDF (4/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
6 Pin Configurations and Functions
NKD
64-Pin WQFN
Top View
www.ti.com
CAP_PLL0 ⁴⁹
MODE_SEL1 ⁵⁰
VDDP12_CH0 ⁵¹
VDDR12_CH0 ⁵²
RIN0+ ⁵³
RIN0- ⁵⁴
CMF 55
VDD33_A 56
VDDR12_CH1 57
RIN1+ 58
RIN1- 59
VDDP12_CH1 60
MODE_SEL0 61
CMLOUTP 62
CMLOUTN 63
CAP_PLL1 64
DS90UH940-Q1
64 WQFN
Top Down View
DAP
32 VDDP12_CSI
31 VDD33_B
30 CSI0_D3+
29 CSI0_D3-
28 CSI0_D2+
27 CSI0_D2-
26 CSI0_D1+
25 _{CSI0_D1-}
24 _{CSI0_D0+}
23 CSI0_D0-
22 _{CSI0_CLK+}
21 _{CSI0_CLK-}
20 _{VDD12_CSI0}
19 _{D_GPIO0/MOSI}
18 _{D_GPIO1/MISO}
17 D_GPIO2/SPLK
Pin Functions
PIN
NAME
NUMBER
I/O, TYPE
DESCRIPTION
MIPI DPHY / CSI-2 OUTPUT PINS - Layout note: for unused CSI outputs, float those pins (do not connect to an external pullup or
pulldown)
CSI0_CLK-
CSI0_CLK+
21
O, DPHY CSI0 Differential clock
22
CSI0_D0-
CSI0_D0+
23
O, DPHY CSI0 Differential pair 0
24
CSI0_D1-
CSI0_D1+
25
O, DPHY CSI0 Differential pair 1
26
CSI0_D2-
CSI0_D2+
27
O, DPHY CSI0 Differential pair 2
28
CSI0_D3-
CSI0_D3+
29
O, DPHY CSI0 Differential pair 3
30
CSI1_CLK-
CSI1_CLK+
34
O, DPHY CSI1 Differential clock
35
CSI1_D0-
CSI1_D0+
36
O, DPHY CSI1 Differential pair 1
37
CSI1_D1-
CSI1_D1+
38
O, DPHY CSI1 Differential pair 2
39
4
Submit Documentation Feedback
Copyright © 2014–2016, Texas Instruments Incorporated
Product Folder Links: DS90UH940-Q1