DS90UH940-Q1 Datasheet, PDF (28/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
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8.3.8.3 GPIO_REG[8:5] Configuration
GPIO_REG[8:5] are register-only GPIOs and may be programmed as outputs or read as inputs through local
register bits only. Where applicable, these bits are shared with I2S pins and will override I2S input if enabled into
GPIO_REG mode. See Table 5 for GPIO enable and configuration.
Note: Local GPIO value may be configured and read either through local register access, or remote register
access through the Low-Speed Bidirectional Control Channel. Configuration and state of these pins are not
transported from serializer to deserializer as is the case for GPIO[3:0].
Description
GPIO_REG8
GPIO_REG7
GPIO_REG6
GPIO_REG5
GPIO3
GPIO2
GPIO1
GPIO0
Table 5. GPIO_REG and GPIO Local Enable and Configuration
Register Configuration
0x21[7:4] = 0x1
0x21[7:4] = 0x9
0x21[7:4] = 0x3
0x21[3:0] = 0x1
0x21[3:0] = 0x9
0x21[3:0] = 0x3
0x20[7:4] = 0x1
0x20[7:4] = 0x9
0x20[7:4] = 0x3
0x20[3:0] = 0x1
0x20[3:0] = 0x9
0x20[3:0] = 0x3
0x1F[3:0] = 0x1
0x1F[3:0] = 0x9
0x1F[3:0] = 0x3
0x1E[7:4] = 0x1
0x1E[7:4] = 0x9
0x1E[7:4] = 0x3
0x1E[3:0] = 0x1
0x1E[3:0] = 0x9
0x1E[3:0] = 0x3
0x1D[3:0] = 0x1
0x1D[3:0] = 0x9
0x1D[3:0] = 0x3
Function
Output, L
Output, H
Input, Read: 0x6F[0]
Output, L
Output, H
Input, Read: 0x6E[7]
Output, L
Output, H
Input, Read: 0x6E[6]
Output, L
Output, H
Input, Read: 0x6E[5]
Output, L
Output, H
Input, Read: 0x6E[3]
Output, L
Output, H
Input, Read: 0x6E[2]
Output, L
Output, H
Input, Read: 0x6E[1]
Output, L
Output, H
Input, Read: 0x6E[0]
8.3.9 SPI Communication
The SPI Control Channel utilizes the secondary link in a 2-lane FPD-Link III implementation. Two possible
modes are available, Forward Channel and Reverse Channel modes. In Forward Channel mode, the SPI Master
is located at the Serializer, such that the direction of sending SPI data is in the same direction as the video data.
In Reverse Channel mode, the SPI Master is located at the Deserializer, such that the direction of sending SPI
data is in the opposite direction as the video data.
The SPI Control Channel can operate in a high speed mode when writing data, but must operate at lower
frequencies when reading data. During SPI reads, data is clocked from the slave to the master on the SPI clock
falling edge. Thus, the SPI read must operate with a clock period that is greater than the round trip data latency.
On the other hand, for SPI writes, data can be sent at much higher frequencies where the MISO pin can be
ignored by the master.
SPI data rates are not symmetrical for the two modes of operation. Data over the forward channel can be sent
much faster than data over the reverse channel.
Note: SPI cannot be used to access Serializer / Deserializer registers.
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