DS90UH940-Q1 Datasheet, PDF (17/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

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DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ. MIN
t_HS-PREPARE
+ t_HS-ZERO
t_HS-PREPARE + time that the
transmitter drives the HS-0 state
prior to transmitting the Sync
sequence
145 +
10*UI
t_HS-SETTLE
t_HS-SKIP
Time interval during which the
HS receiver shall ignore any
Data Lane HS transitions,
starting from the beginning of t_HS-
SETTLE
Time interval during which the
HS-RX should ignore any
transitions on the Data Lane,
following a HS burst. The end
point of the interval is defined as
the beginning of the LP-11 state
following the HS burst.
85 +
6*UI
40
t_HS-TRAIL
Data Lane HS Exit
60 +
4*UI
t_LPX
Transmitted length of LP state
50
t_WAKEUP
Recovery Time from Ultra Low
Power State (ULPS)
1
TYP
MAX UNIT
ns
145 +
10*UI
ns
55 +
4*UI
ns
ns
ns
ms
7.10 Timing Diagrams and Test Circuits
CSI0_CLK±,
CSI1_CLK±
CSI0_D1±, CSI0_D3±,
CSI1_D1±, CSI1_D3±
CSI0_D0±, CSI0_D2±,
CSI1_D0±, CSI1_D2±
Cycle N
Cycle N+1
+VOD
-VOD
+VOD
-VOD
+VOD
-VOD
Figure 1. Checkerboard Data Pattern
EW
VOD (+)
RIN
(Diff.)
EH
0V
EH
t_BIT (1 UI)
Figure 2. CML Output Driver
VOD (-)
t_CLH
80%
20%
t_CHL
Figure 3. LVCMOS Transition Times
V_DDIO
GND
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