DS90UH940-Q1 Datasheet, PDF (42/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
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8.4.5 MIPI CSI-2 Output Data Formats
The DS90UH940-Q1 CSI-2 Tx supports multiple data types. These can be seen in Table 10.
Table 10. CSI-2 Output Data Formats⁽¹⁾
Data Format
RGB888
RGB666
RGB565
YUV420
YUV420 8-bit
YUV422 8-bit
RAW8
CSI-2 Data Type
[5:0]
0x24
Reg0x6B [3:2]
IFMT
00
0x23
00
0x22
00
0x1A
00
0x18
00
0x1E
00
0x2A
11
RAW10
0x2B
11
RAW12
0x2C
11
YUV420 8-bit (CSPS)
0x1C
00
Reg0x6B [7:4]
OFMT
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Description
RGB888 image data – using 24-bit container for
RGB 24-bpp
RGB666 image data
RGB565 image data
YUV4:2:0 image data, Legacy YUV420 8-bit
YUV4:2:0 image data
YUV4:2:2 image data
RAW Bayer, 8-bit image data D[0:7] of Serializer
inputs are used as RAW data; Alignment is
configured with CSIIA_{0x6C}_0x09 [4]
RAW Bayer, 10-bit image data D[0:9] of Serializer
inputs are used as RAW data; Alignment is
configured with CSIIA_{0x6C}_0x09 [4]
RAW Bayer, 12-bit image data D[0:11] of Serializer
inputs are used as RAW data; Alignment is
configured with CSIIA_{0x6C}_0x09 [4]
YUV4:2:0 image data, YUV420 Chroma Shifted
Pixel Sampling
(1) Note: Color space conversion is only available from RGB to YUV.
8.4.6 Non-Continuous / Continuous Clock
DS90UH940-Q1 D-PHY supports Continuous clock mode and Non-Continuous clock mode on the CSI-2
interface. Default mode is Non-Continuous Clock mode, where the Clock Lane enters in LP mode between the
transmissions of data packets. Non-continuous clock mode will only be non-continuous during the vertical
blanking period for lower PCLK rates. For higher PCLK rates, the clock will be non-continuous between line and
frame packets. Operating modes are configurable through 0x6A [1].
Clock lane enters LP11 during horizontal blanking if the horizontal blanking period is longer than the overhead
time to start/stop the clock lane. There is auto-detection of the length of the horizontal blank period. The fixed
threshold is 96 PCLK cycles.
8.4.7 Ultra Low Power State (ULPS)
The DS90UH940-Q1 supports the MIPI defined Ultra-Low Power State (ULPS). DS90UH940-Q1 D-PHY lanes
will enter ULPS mode upon software standby mode through 0x6A [2] generated by the processor. When ULPS is
issued, all active CSI-2 lanes including the clock and data lanes of the enabled CSI-2 port are put in ULPS
according to the MIPI DPHY protocol. D-PHY can reduce power consumption by entering ULPS mode. Ultra Low
Power State is exited by means of a Mark-1 state with a length TWAKEUP followed by a Stop state.
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