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| DS90UH940-Q1 Datasheet, PDF (20/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer | |||
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DS90UH940-Q1
SNLS478A â NOVEMBER 2014 â REVISED JANUARY 2016
Timing Diagrams and Test Circuits (continued)
Clock Lane
Dp/Dn
TCLK-POST
VIH(min)
VIL(max)
TEOT
TCLK-MISS
Disconnect
Terminator
TCLK-SETTLE
TCLK-TERM-EN
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TCLK-TRAIL
Data Lane
Dp/Dn
Disconnect
Terminator
THS-EXIT
TLPX
TCLK-ZERO
TCLK-PREPARE
TCLK-PRE
TLPX
THS-PREPARE
VIH(min)
VIL(max)
THS-SKIP
TD-TERM-EN
THS-SETTLE
Figure 12. Switching the Clock Lane between Clock Transmission and Low-Power Mode
VS
(internal Node)
DE
(internal Node)
1st
Line
2nd
Line
Vertical Blanking
Last
Line
CSI0_D[3:0]±
or
CSI1_D[3:0]±
LPS
FS
Line
Packet
Line
Packet
Line
Packet
Line
Packet
1 to 216 tLPX
FE
FS
LPS
LPS
LPS
LPS
LPS LPS
LPS
Line
Packet
Frame
Sync
Packet
Figure 13. Long Line Packets and Short Frame Sync Packets
20
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