DS90UH940-Q1 Datasheet, PDF (29/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

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DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
8.3.9.1 SPI Mode Configuration
SPI is configured over I2C using the High-Speed Control Channel Configuration (HSCC_CONTROL) register,
0x43 (Table 12). HSCC_MODE (0x43[2:0]) must be configured for either High-Speed, Forward Channel SPI
mode (110) or High-Speed, Reverse Channel SPI mode (111).
8.3.9.2 Forward Channel SPI Operation
In Forward Channel SPI operation, the SPI master located at the Serializer generates the SPI Clock (SPLK),
Master Out / Slave In data (MOSI), and active low Slave Select (SS). The Serializer oversamples the SPI
signals directly using the video pixel clock. The three sampled values for SPLK, MOSI, and SS are each sent on
data bits in the forward channel frame. At the Deserializer, the SPI signals are regenerated using the pixel
clock. In order to preserve setup and hold time, the Deserializer will hold MOSI data while the SPLK signal is
high. In addition, it delays SPLK by one pixel clock relative to the MOSI data, increasing setup by one pixel
clock.
SERIALIZER
SS
SPLK
MOSI
D0
D1
D2
D3
DN
SS
DESERIALIZER
SPLK
MOSI
D0
D1
D2
D3
DN
Figure 20. Forward Channel SPI Write
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