DS90UH940-Q1 Datasheet, PDF (15/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

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DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
7.9 Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ. MIN
TYP
MAX UNIT
HSTX DRIVER
HSTX_DBR Data bit rate⁽¹⁾
fCLK
DDR Clock frequency⁽¹⁾
ΔV_CMTX(HF)
ΔV_CMTX(LF)
t_RHS
t_FHS
Common mode voltage
variations HF⁽¹⁾
Common mode voltage
variations LF⁽¹⁾
20% to 80% Rise and Fall HS⁽¹⁾
MIPI 2 Lanes
MIPI 4 Lanes
MIPI 2 Lanes
MIPI 4 Lanes
Above 450MHz
Between 50 and 450MHz
HS bit rates ≤ 1 Gbps (UI ≥ 1 ns)
CSI0_D0±
CSI0_D1±
CSI0_D2±
CSI0_D3±
CSI1_D0±
CSI1_D1±
CSI1_D2±
CSI1_D3±
CSI0_CLK±
CSI1_CLK±
HS bit rates > 1 Gbps (UI < 1 ns)
350
175
175
87.5
1344
1190
672
595
Mbps
MHz
15 mV_RMS
25 mV_RMS
0.3 UI
0.35 UI
Applicable for all HS bit rates.
However, to avoid excessive
radiation, bit rates ≤ 1 Gbps (UI
100
≥ 1 ns), should not use values
below 150 ps
SDD_TX
TX differential return loss⁽¹⁾
f_LPMAX
f_H
f_MAX
LPTX DRIVER
t_RLP
Rise Time LP^{(2) (3)}
15% to 85% rise time
CSI0_D0±
t_FLP
t_REOT
Fall Time LP^{(2) (3)}
Rise Time Post-EoT^{(1) (3)}
15% to 85% fall time
30%-85% rise time
CSI0_D1±
CSI0_D2±
CSI0_D3±
t_LP-PULSE-TX Pulse width of the LP exclusive- First LP exclusive-OR clock
CSI1_D0±
OR clock^{(1) (3)}
pulse after Stop state or last
CSI1_D1±
40
pulse before Stop state
CSI1_D2±
All other pulses
CSI1_D3±
20
t_LP-PER-TX
Period of the LP exclusive-OR
clock ⁽¹⁾
CSI0_CLK±
CSI1_CLK±
90
DV/DtSR Slew rate^{(2) (3)}
Cload = 0pF
ps
-18 dB
-9 dB
25 ns
25 ns
35 ns
ns
ns
ns
500 mV/ns
Cload = 5pF
300 mV/ns
Cload = 20pF
250 mV/ns
Cload = 70pF
150 mV/ns
Cload = 0 to 70pF (Falling Edge
Only)
30
mV/ns
Cload = 0 to 70pF (Rising Edge
Only)
30
mV/ns
C_LOAD
Load capacitance⁽³⁾
Cload = 0 to 70pF (Rising Edge
Only)
30 -
0.075*(V
O,INST -
700)
0
mV/ns
70 pF
(1) Specification is ensured by design and is not tested in production.
(2) This parameter is specified by characterization and is not tested in production.
(3) C_LOAD includes the low-frequency equivalent transmission line capacitance. The capacitance of TX and RX are assumed to always be
<10 pF. The distributed line capacitance can be up to 50 pF for a transmission line with 2ns delay.
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