DS90UH940-Q1 Datasheet, PDF (65/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

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DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
Register Maps (continued)
ADD
(hex)
0x65
0x66
0x67
0x68
0x69
Register
Name
PGCFG
PGIA
PGID
PGDBG
PGTSTDAT
Table 12. Serial Control Bus Registers (continued)
Bit(s) Function
7:5 RESERVED
4
PATGEN_18B
Type
R
RW
3
PATGEN_
RW
EXTCLK
2
PATGEN_TSEL RW
1
PATGEN_INV RW
0
PATGEN_
RW
ASCRL
7:0 PATGEN_IA
RW
7:0 PATGEN_ID
RW
7:4 RESERVED
RW
3
PATGEN_BIST_ RW
EN
2:0 RESERVED
RW
7
PATGEN_BIST_ R
ERR
6:0 RESERVED
R
Default
Description
Value (hex)
0
Reserved
0
18-bit Mode Select:
1: Enable 18-bit color pattern generation. Scaled patterns will
have 64 levels of brightness and the R, G, and B outputs use
the six most significant color bits.
0: Enable 24-bit pattern generation. Scaled patterns use 256
levels of brightness.
This bit has no effect in external timing mode (PATGEN_TSEL
= 0).
0
Select PCLK of Pattern generator
1: Selects the external pixel clock when using internal timing.
0: Selects the internal divided clock when using internal timing.
This bit has no effect in external timing mode (PATGEN_TSEL
= 0).
0
Timing Select Control:
1: The Pattern Generator creates its own video timing as
configured in the Pattern Generator Total Frame Size, Active
Frame Size, Horizontal Sync Width, Vertical Sync Width,
Horizontal Back Porch, Vertical Back Porch, and Sync
Configuration registers.
0: the Pattern Generator uses external video timing from the
pixel clock, Data Enable, Horizontal Sync, and Vertical Sync
signals.
0
Enable Inverted Color Patterns:
1: Invert the color output.
0: Do not invert the color output.
0
Auto-Scroll Enable:
1: The Pattern Generator will automatically move to the next
enabled pattern after the number of frames specified in the
Pattern Generator Frame Time (PGFT) register.
0: The Pattern Generator retains the current pattern.
0
Indirect Address:
This 8-bit field sets the indirect address for accesses to
indirectly-mapped registers. It should be written prior to reading
or writing the Pattern Generator Indirect Data register.
See TI App Note AN-2198.
0
Indirect Data:
When writing to indirect registers, this register contains the data
to be written. When reading from indirect registers, this register
contains the readback value.
See TI App Note AN-2198.
0
Reserved
0
Pattern Generator BIST Enable:
Enables Pattern Generator in BIST mode. Pattern Generator
will compare received video data with local generator pattern.
Upstream device must be programmed to the same pattern.
0
Reserved
0
Pattern Generator BIST Error Flag
During Pattern Generator BIST mode, this bit indicates if the
BIST engine has detected errors. If the BIST Error Count
(available in the Pattern Generator indirect registers) is non-
zero, this flag will be set.
0
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