DS90UH940-Q1 Datasheet, PDF (19/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

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Timing Diagrams and Test Circuits (continued)
DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
I2S_CLK
I2S_WC
I2S_D[A,B,C,D]
t_I2S
t_LC,I2S
t_SR,I2S
t_HC,I2S
V_IH
V_IL
t_HR,I2S
Figure 9. I2S Timing
Clock Lane
CSI[1:0]_D[3:0]+
CSI[1:0]_D[3:0]-
CSI[1:0]_CLK+
0.5UI +
tskew
CSI[1:0]_CLK-
1 UI
Figure 10. Clock and Data Timing in HS Transmission
Data Lane
Dp/Dn
VIH(min)
VIL(max)
T_LPX
T_HS-ZERO
THS-PREPARE
T_HS-SYNC
LP-11
T_D-TERM-EN
LP-01
LP-00
T_HS-SETTLE
Capture
1^st Data Bit
Figure 11. High Speed Data Transmission Burst
Disconnect
Terminator
T_REOT
T_HS-SKIP LP-11
T_EOT
T_HS-TRAIL
T_HS-EXIT
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