DS90UH940-Q1 Datasheet, PDF (44/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
8.5 Programming
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8.5.1 Serial Control Bus
The device may also be configured by the use of a I2C compatible serial control bus. Multiple devices may share
the serial control bus (up to 8 device addresses supported). The device address is set via a resistor divider (R1
and R2 — see Figure 32 below) connected to the IDx pin.
VDD33
HOST
SCL
SDA
VDDIO
R1
VR2
IDx
4.7k
4.7k
R2
DES
SCL
SDA
To other
Devices
Figure 32. Serial Control Bus Connection
The serial control bus consists of two signals, SCL and SDA. SCL is a Serial Bus Clock Input. SDA is the Serial
Bus Data Input / Output signal. Both SCL and SDA signals require an external pull-up resistor to 1.8 V or 3.3 V
VDDIO. For most applications, a 4.7kΩ pull-up resistor to VDD33 is recommended. However, the pull-up resistor
value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or
driven Low.
The IDx pin configures the control interface to one of 8 possible device addresses. A pull-up resistor and a pull-
down resistor may be used to set the appropriate voltage ratio between the IDx input pin (V_R2) and VDD33, each
ratio corresponding to a specific device address. See Table 11 below.
#
Ideal Ratio
V_R2 / VDD33
1
0
2
0.169
3
0.230
4
0.295
5
0.376
6
0.466
7
0.556
8
0.801
Table 11. Serial Control Bus Addresses for IDx
Ideal V_R2
(V)
0
0.559
0.757
0.974
1.241
1.538
1.835
2.642
Suggested Resistor Suggested Resistor
R1 kΩ (1% tol)
R2 kΩ (1% tol)
Open
40.2 or >10
232
47.5
107
31.6
113
47.5
113
68.1
107
93.1
90.9
113
45.3
182
7-bit Address
0x2C
0x2E
0x30
0x32
0x34
0x36
0x38
0x3C
8-bit Address
0x58
0x5C
0x60
0x64
0x68
0x6C
0x70
0x78
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See
Figure 33
SDA
SCL
S
START condition, or
START repeat condition
P
STOP condition
Figure 33. START and STOP Conditions
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