DS90UH940-Q1 Datasheet, PDF (2/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
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Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Applications Diagram ............................................ 1
5 Revision History..................................................... 2
6 Pin Configurations and Functions ....................... 4
7 Specifications......................................................... 9
7.1 Absolute Maximum Ratings ...................................... 9
7.2 ESD Ratings—JEDEC .............................................. 9
7.3 ESD Ratings—IEC and ISO...................................... 9
7.4 Recommended Operating Conditions....................... 9
7.5 Thermal Information ................................................ 10
7.6 DC Electrical Characteristics .................................. 10
7.7 AC Electrical Characteristics................................... 13
7.8 Timing Requirements for the Serial Control Bus .... 14
7.9 Switching Characteristics ........................................ 15
7.10 Timing Diagrams and Test Circuits....................... 17
7.11 Power Sequence................................................... 22
7.12 Typical Characteristics .......................................... 23
8 Detailed Description ............................................ 24
8.1 Overview ................................................................. 24
8.2 Functional Block Diagram ....................................... 25
8.3 Feature Description................................................. 25
8.4 Device Functional Modes........................................ 37
8.5 Programming........................................................... 44
8.6 Register Maps ......................................................... 47
9 Application and Implementation ........................ 70
9.1 Application Information ......................................... 70
9.2 Typical Applications ................................................ 70
10 Power Supply Recommendations ..................... 75
10.1 Power Up Requirements and PDB Pin ................. 75
11 Layout................................................................... 75
11.1 Layout Guidelines ................................................. 75
11.2 Layout Example .................................................... 77
12 Device and Documentation Support ................. 79
12.1 Documentation Support ....................................... 79
12.2 Community Resources.......................................... 79
12.3 Trademarks ........................................................... 79
12.4 Electrostatic Discharge Caution ............................ 79
12.5 Glossary ................................................................ 79
13 Mechanical, Packaging, and Orderable
Information ........................................................... 79
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (November 2014) to Revision A
Page
• Added shared pins description on SPI pins .......................................................................................................................... 5
• Added shared pins description on GPIO pins ....................................................................................................................... 6
• Added shared pins description on D_GPIO pins ................................................................................................................... 6
• Added shared pins description on register only GPIO pins. Changed "Local register control only" to "I2C register
control only". .......................................................................................................................................................................... 6
• Added shared pins description on slave mode I2S pins ....................................................................................................... 7
• Added shared pins description on master mode I2S pins ..................................................................................................... 7
• Added legend on I/O TYPE .................................................................................................................................................... 8
• Moved Storage Temperature Range from ESD to Absolute Maximum Ratings table .......................................................... 9
• Added ESD Ratings table....................................................................................................................................................... 9
• Changed IDD12Z limit from 11mA to 30mA per PE re-characterization ............................................................................. 12
• Changed Fast Plus Mode t_SP maximum from 20ns to 50ns ................................................................................................ 14
• Added Power Sequence section ......................................................................................................................................... 22
• Deleted MODE, CSI LANE, REPLICATE columns in MODE_SEL0 table .......................................................................... 40
• Deleted MODE column. Added (CSI PORT) to CSI_SEL column in MODE_SEL1 table.................................................... 40
• Changed default value from "0" to "1" in register 0x01[2] ................................................................................................... 47
• Added description to register 0x01[1] "Registers which are loaded by pin strap will be restored to their original strap
value when this bit is set. These registers show ‘Strap’ as their default value in this table." ............................................. 47
• Added to 0x02[7] in Description column "A Digital reset 0x01[0] should be asserted after toggling Output Enable bit
LOW to HIGH" ..................................................................................................................................................................... 47
• Added "Loaded from remote SER" in register 0x07[7:1] function column............................................................................ 49
• Changed signal detect bit to reserved in register 0x1C[1] ................................................................................................... 52
• Changed "0" to "0/1" in register RW column of 0x1C[1] ...................................................................................................... 52
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