DS90UH940-Q1 Datasheet, PDF (38/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
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Device Functional Modes (continued)
8.4.1.4 2-lane FPD-Link III Input, 2 MIPI lanes Output
In this configuration the PCLK rate embedded is split into 2-lane FPD-Link III frame and can range from 25 MHz
to 48 MHz, resulting in a link rate of 875 Mbps (35 bit * 25 MHz) to 1.680 Gbps (35 bit * 48 MHz). The embedded
datastreams from the received FPD-Link III inputs are merged in HS mode to form packets that carry the video
stream. Each MIPI data lane will operate at a speed of 14 * PCLK frequency, resulting in a data rate of 700 Mbps
to 1344 Mbps. The corresponding MIPI transmit clock rate will operate between 350 MHz to 672 MHz.
8.4.1.5 1- or 2-lane FPD-Link III Input, 2 or 4 MIPI lanes Output in Replicate
Same as 1- or 2-lane FPD-Link III Input(s), duplicates the MIPI CSI-2 lanes on CSI1_D[3:0] and CSI1_CLK
outputs.
8.4.2 MODE_SEL[1:0]
Configuration of the device may be done via the MODE_SEL[1:0] input pins, or via the configuration register bits.
A pull-up resistor and a pull-down resistor of suggested values may be used to set the voltage ratio of the
MODE_SEL[1:0] inputs (V_R4) and VDD33 to select one of the other 8 possible selected modes. See Table 8 and
Table 9. Possible configurations are shown in Figure 27.
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