DS90UH940-Q1 Datasheet, PDF (58/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
www.ti.com
Register Maps (continued)
Table 12. Serial Control Bus Registers (continued)
ADD
(hex)
0x24
Register
Name
Bit(s)
BIST Control 7:6
Function
BIST_OUT_
MODE
Type
RW
5:4 AUTO_OSC_FR RW
EQ
3
BIST PIN
RW
CONFIG
2:1 BIST CLOCK
RW
SOURCE
0
BIST_EN
RW
0x25
BIST
ERROR
COUNT
7:0 BIST ERROR
R
COUNT
0x26 SCL High 7:0 SCL HIGH TIME RW
Time
0x27 SCL Low
Time
7:0 SCL LOW TIME RW
Default
Description
Value (hex)
0
BIST Output Mode
00 : No toggling
01 : Alternating 1/0 toggling
1x : Toggle based on BIST data
0
When register 0x02 bit 5 (AUTO)CLOCK_EN) is set, this field
controls the nominal frequency of the oscillator-based receive
clock.
00: 50 MHz
01: 25 MHz
10: 10 MHz
11: Reserved
1
Bist Configured through Pin.
1: Bist configured through pin.
0: Bist configured through bits 2:0 in this register
0
BIST Clock Source
This register field selects the BIST Clock Source at the
Serializer. These register bits are automatically written to the
CLOCK SOURCE bits (register offset 0x14) in the Serializer
after BIST is enabled. See the appropriate Serializer register
descriptions for details.
00: External Pixel Clock
01: Internal Pixel Clock
1x: Internal Pixel Clock
0
BIST Control
1: Enabled
0: Disabled
0
Bist Error Count
Returns BIST error count for selected port. Port selected is
based on the PORT_SEL control in the DUAL_RX_CTL register
0x34 [1:0].
0x83
I2C Master SCL High Time
This field configures the high pulse width of the SCL output
when the De-Serializer is the Master on the local I2C bus. Units
are 50 ns for the nominal oscillator clock frequency. The default
value is set to provide a minimum 5us SCL high time with the
internal oscillator clock running at 26MHz rather than the
nominal 20MHz.
0x84
I2C SCL Low Time
This field configures the low pulse width of the SCL output
when the De-Serializer is the Master on the local I2C bus. This
value is also used as the SDA setup time by the I2C Slave for
providing data prior to releasing SCL during accesses over the
Bidirectional Control Channel. Units are 50 ns for the nominal
oscillator clock frequency. The default value is set to provide a
minimum 5us SCL low time with the internal oscillator clock
running at 26MHz rather than the nominal 20MHz.
58
Submit Documentation Feedback
Copyright © 2014–2016, Texas Instruments Incorporated
Product Folder Links: DS90UH940-Q1