DS90UH940-Q1 Datasheet, PDF (59/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

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DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
Register Maps (continued)
ADD
(hex)
0x28
Register
Name
Datapath
Control 2
0x2B I2S Control
0x2E PCLK Test
Mode
Table 12. Serial Control Bus Registers (continued)
Bit(s) Function
Type
7
OVERRIDE FC RW
CONFIG
6
RESERVED
RW
5
VIDEO_
RW
DISABLED
(Loaded from
remote SER)
4
DUAL_LINK
R
(Loaded from
remote SER)
3
ALTERNATE I2S RW
ENABLE
(Loaded from
remote SER)
2
I2S DISABLED RW
(Loaded from
remote SER)
1
28BIT VIDEO
RW
(Loaded from
remote SER)
0
I2S SURROUND RW
(Loaded from
remote SER)
7:4 RESERVED
RW
3
I2S FIFO
R
OVERRUN
STATUS
2
I2S FIFO
R
UNDERRUN
STATUS
1
I2S FIFO
RW
ERROR RESET
0
I2S DATA
RW
FALLING EDGE
7
EXTERNAL
RW
PCLK
6:0 RESERVED
RW
Default
Description
Value (hex)
0
1: Disable loading of this register from the forward channel,
keeping locally witten values intact
0: Allow forward channel loading of this register
0
Reserved
0
Forward channel video disabled
0 : Normal operation
1 : Video is disabled, control channel is enabled
This is a status bit only, indicating the forward channel is not
sending active video. In this mode, the control channel and
GPIO functions are enabled. Setting OVERRIDE_FC_CONFIG
will prevent this bit from changing.
1: Dual Link mode enabled
0: Single Link mode enabled
This bit will always be loaded from forward channel and cannot
be written locally. To force DUAL_LINK receive mode, use the
RX_PORT_SEL register (address 0x34)
0
1: Enable alternate I2S output on GPIO1 (word clock) and
GPIO0 (data)
0: Normal Operation
0
1: I2S DISABLED
0: Normal Operation
0
1: 28 bit Video enable. i.e. HS, VS, DE are present in forward
channel.
0: Normal Operation
0
1: I2S Surround enabled
0: I2S Surround disabled
0
Reserved
0
I2S FIFO Overrun Status
0
I2S FIFO Underrun Status
0
I2S Fifo Error Reset
1: Clears FIFO Error
0
I2S Clock Edge Select
1: I2S Data is strobed on the Rising Clock Edge.
0: I2S Data is strobed on the Falling Clock Edge.
0
Select pixel clock from BISTC input
0
Reserved
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