DS90UH940-Q1 Datasheet, PDF (16/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
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Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
DATA-CLOCK TIMING SPECIFICATIONS ⁽¹⁾ (Figure 10)
PIN/FREQ. MIN
TYP
UI_INST
ΔUI
t_SKEW(TX)
UI instantaneous
UI variation
PCLK = 25 - 96MHz
Data to Clock Skew (measured
at transmitter)
Skew between clock and data
from ideal center
fCLK = CSI-2 DDR Clock
frequency
UI ≥ 1ns
UI < 1ns
Data rate ≤ 1 Gbps
Data rate > 1 Gbps
CSI-2 TIMING SPECIFICATIONS ⁽¹⁾ (Figure 11, Figure 12)
CSI0_D0±
CSI0_D1±
CSI0_D2±
CSI0_D3±
CSI1_D0±
CSI1_D1±
CSI1_D2±
CSI1_D3±
CSI0_CLK±
CSI1_CLK±
1/(fCLK
* 2)
-10%
-5%
-0.15
-0.2
t_CLK-MISS
t_CLK-POST
Timeout for receiver to detect
absence of Clock transitions and
disable the Clock Lane HS-RX
HS exit
t_CLK-PRE
t_CLK-
PREPARE
t_CLK-SETTLE
Time HS clock shall be driver
prior to any associated Data
Lane beginning the transition
from LP to HS mode
Clock Lane HS Entry
Time interval during which the
HS receiver shall ignore any
Clock Lane HS transitions
CSI0_D0±
CSI0_D1±
CSI0_D2±
CSI0_D3±
CSI1_D0±
CSI1_D1±
CSI1_D2±
CSI1_D3±
CSI0_CLK±
CSI1_CLK±
60
60 +
52*UI
8
38
95
t_CLK-TERM-EN Time-out at Clock Lane Display
Module to enable HS
Termination
Time for
Dn to
reach
VTERM-
EN
t_CLK-TRAIL Time that the transmitter drives
the HS-0 state after the last
payload clock bit of a HS
60
transmission burst
t_CLK-
PREPARE ⁺
t_CLK-ZERO
t_D-TERM-EN
TCLK-PREPARE + time that the
transmitter drives the HS-0 state
prior to starting the Clock
Time for the Data Lane receiver
to enable the HS line termination
t_EOT
Transmitted time interval from see⁽⁴⁾
the start of t_HS-TRAIL to the start
of the LP-11 state following a HS
burst
300
Time for
Dn to
reach V-
TERM-
EN
t_HS-EXIT
Time that the transmitter drives
LP=11 following a HS burst
100
t_HS-PREPARE Data Lane HS Entry
40 +
4*UI
MAX UNIT
UI
10%
5%
0.15
UI
UI
UI_INST
0.2 UI_INST
ns
ns
UI
95 ns
300 ns
38 ns
ns
ns
35 +
4*UI
ns
105 +
12*UI
ns
ns
85 +
6*UI
ns
(4) (a) 1280x720p60; PCLK = 74.25MHz; 4 MIPI lanes reg0x6c=0x02; reg0x6d=0x84
(b) 1280x720p60; PCLK = 74.25MHz; 2 MIPI lanes reg0x6c=0x02; reg0x6d=0x89
(c) 640x480p60; PCLK = 25MHz; 4 MIPI lanes reg0x6c=0x02; reg0x6d=0x82
(d) 640x480p60; PCLK = 25MHz; 2 MIPI lanes reg0x6c=0x02; reg0x6d=0x83
(e) Other video formats may require additional register configuration.
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