DS90UH940-Q1 Datasheet, PDF (22/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
7.11 Power Sequence
t₀
VDD33
GND
t₃
www.ti.com
VDDIO
GND
t₄
t₁
VDD12
GND
t₂
PDB^(*)
GND
V_{PDB_HIGH}
V_{PDB_LOW}
VDDIO
t₅
(*) _{It is recommended to assert PDB (active High) with a microcontroller rather than an RC filter}
network to help ensure proper sequencing of PDB pin after settling of power supplies.
Figure 16. Power Sequence
Symbol
VDDIO
VDD33
VDD12
V_{PDB_LOW}
V_{PDB_HIGH}
t₀
t₃
Table 1. Power-Up Sequencing Constraints
Description
Test Conditions
Min
Typ
Max
Units
VDDIO voltage range
3.0
3.6
V
1.71
1.89
V
VDD33 voltage range
3.0
3.6
V
VDD12 voltage range
1.14
1.26
V
PDB LOW threshold
VDDIO = 3.3V ± 10%
0.8
Note: V_PDB should not exceed
limit for respective I/O voltage
before 90% voltage of VDD12
VDDIO = 1.8V ± 5%
0.35 *
VDDIO
V
PDB HIGH threshold
VDDIO = 3.3V ± 10%
VDDIO = 1.8V ± 5%
2.0
0.65 *
V
VDDIO
VDD33 rise time
These time constants are specified for
rise time of power supply voltage ramp
(10% - 90%)
<1.5
ms
VDDIO rise time
These time constants are specified for
rise time of power supply voltage ramp
(10% - 90%)
<1.5
ms
22
Submit Documentation Feedback
Copyright © 2014–2016, Texas Instruments Incorporated
Product Folder Links: DS90UH940-Q1