DS90UH940-Q1 Datasheet, PDF (52/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
www.ti.com
Register Maps (continued)
Table 12. Serial Control Bus Registers (continued)
ADD
(hex)
0x1A
Register
Name
GPIO[9] and
Global GPIO
Config
Bit(s)
7
Function
Type
GLOBAL GPIO RW
OUTPUT VALUE
6
RESERVED
RW
5
GLOBAL GPIO RW
FORCE DIR
4
GLOBAL GPIO RW
FORCE EN
3
GPIO9 OUTPUT RW
VALUE
2
RESERVED
RW
1
GPIO9 DIR
RW
0
GPIO9 EN
RW
0x1B Frequency 7:0
Counter
Frequency Count RW
0x1C General
Status
7:5 RESERVED
R
4
DUAL_RX_STS R
3
I2S LOCKED
R
2
RESERVED
R
1
RESERVED
R
0
LOCK
R
Default
Description
Value (hex)
0
Global GPIO Output Value
This value is output on each GPIO pin when the individual pin is
not otherwise enabled as a GPIO and the global GPIO direction
is Output
0
Reserved
0
The GLOBAL GPIO DIR and GLOBAL GPIO EN bits configure
the pad in input direction or output direction for functional mode
0
or GPIO mode. The GLOBAL bits are overridden by the
individual GPIO DIR and GPIO EN bits.
{GLOBAL GPIO DIR, GLOBAL GPIO EN}
00: Functional mode; output
10: Tri-state
01: Force mode; output
11: Force mode; input
0
Local GPIO Output Value
This value is output on the GPIO pin when the GPIO function is
enabled, the local GPIO direction is Output, and remote GPIO
control is disabled.
0
Reserved
0
The GPIO DIR and GPIO EN bits configure the pad in input
0
direction or output direction for functional mode or GPIO mode.
{GPIO DIR, GPIO EN}
00: Functional mode; output
10: Tri-state
01: GPIO mode; output
11: GPIO mode; input
0
Frequency Counter control
A write to this register will enable a frequency counter to count
the number of pixel clock during a specified time interval. The
time interval is equal to the value written multiplied by the
oscillator clock period (nominally 50ns). A read of the register
returns the number of pixel clock edges seen during the
enabled interval. The frequency counter will freeze at 0xff if it
reaches the maximum value. The frequency counter will provide
a rough estimate of the pixel clock period. If the pixel clock
frequency is known, the frequency counter may be used to
determine the actual oscillator clock frequency.
0
Reserved.
0
Receiver Dual Link Status:
This bit indicates the current operating mode of the FPD-Link III
Receive port
1: 2-lane mode active
0: 1-lane mode active
0
I2S LOCK STATUS
0: I2S PLL controller not locked
1: I2S PLL controller locked to input I2S clock
0
Reserved.
0/1
Reserved.
0
De-Serializer CDR, PLL's clock to recovered clock frequency
1: De-Serializer locked to recovered clock
0: De-Serializer not locked
In Dual Link mode, this indicates both channels are locked.
52
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