DS90UH940-Q1 Datasheet, PDF (27/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

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DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
releases the INTB_IN (pin 4) on the Deserializer. The system is now ready to return to step (2) at next falling
edge of INTB_IN.
8.3.8 General-purpose I/O
8.3.8.1 GPIO[3:0] and D_GPIO[3:0] Configuration
In normal operation, GPIO[3:0] may be used as general purpose IOs in either forward channel (outputs) or back
channel (inputs) mode. GPIO and D_GPIO modes may be configured from the registers (Table 11). The same
registers configure either GPIO or D_GPIO, depending on the status of PORT1_SEL and PORT0_SEL bits
(0x34[1:0]). D_GPIO operation requires 2-lane FPD-Link III mode. Consult the appropriate Serializer datasheet
for details on D_GPIO configuration. Note: if paired with a DS90UH925Q-Q1serializer, the devices must be
configured into 18-bit mode to allow usage of GPIO pins on the serializer. To enable 18-bit mode, set serializer
register 0x12[2] = 1. 18-bit mode will be auto-loaded into the deserializer from the serializer. See Table 3 for
GPIO enable and configuration.
Description
GPIO3 / D_GPIO3
GPIO2 / D_GPIO2
GPIO1 / D_GPIO1
GPIO0 / D_GPIO0
Table 3. GPIO Enable and Configuration
Device
Serializer
Deserializer
Serializer
Deserializer
Serializer
Deserializer
Serializer
Deserializer
Forward Channel
0x0F[3:0] = 0x3
0x1F[3:0] = 0x5
0x0E[7:4] = 0x3
0x1E[7:4] = 0x5
0x0E[3:0] = 0x3
0x1E[3:0] = 0x5
0x0D[3:0] = 0x3
0x1D[3:0] = 0x5
Back Channel
0x0F[3:0] = 0x5
0x1F[3:0] = 0x3
0x0E[7:4] = 0x5
0x1E[7:4] = 0x3
0x0E[3:0] = 0x5
0x1E[3:0] = 0x3
0x0D[3:0] = 0x5
0x1D[3:0] = 0x3
The input value present on GPIO[3:0] or D_GPIO[3:0] may also be read from register, or configured to local
output mode (Table 11).
8.3.8.2 Back Channel Configuration
The D_GPIO[3:0] pins can be configured to obtain different sampling rates depending on the mode as well as
back channel frequency. The mode is controlled by register 0x43 (Table 11). The back channel frequency can be
controlled several ways:
1. Register 0x23[6] sets the divider that controls the back channel frequency based on the internal oscillator.
0x23[6] = 0 sets the divider to 4 and 0x23[6] = 1 sets the divider to 2. As long as BC_HS_CTL (0x23[4]) is
set to 0, the back channel frequency would be either 5 Mbps or 10Mbps based on this bit.
2. Register 0x23[4] enables the high-speed back channel. This can also be pin-strapped via MODE_SEL1
(SeeTable 4). This bit overrides 0x23[6], and sets the divider for the back channel frequency to 1. Setting this
bit to 1 sets the back channel frequency to 20 Mbps.
The back channel frequency has variation of ±20%. Note: The back channel frequency must be set to 5 Mbps
when paired with a DS90UH925Q-Q1, DS90UH925AQ-Q1, or DS90UH927Q-Q1. See Table 4 for details about
configuring the D_GPIOs in various modes.
HSCC_MODE
(0x43[2:0])
000
011
010
001
Mode
Normal
Fast
Fast
Fast
Table 4. Back Channel D_GPIO Effective Frequency
Number of
D_GPIOs
Samples per
Frame
D_GPIO Effective Frequency⁽¹⁾ (kHz)
5 Mbps BC⁽²⁾ 10 Mbps BC⁽³⁾ 20 Mbps BC⁽⁴⁾
4
1
33
66
133
4
6
200
400
800
2
10
333
666
1333
1
15
500
1000
2000
(1) The effective frequency assumes the worst case back channel frequency (-20%) and a 4X sampling rate.
(2) 5 Mbps corresponds to BC FREQ SELECT = 0 & BC_HS_CTL = 0
(3) 10 Mbps corresponds to BC FREQ SELECT = 1 & BC_HS_CTL = 0
(4) 20 Mbps corresponds to BC FREQ SELECT = X & BC_HS_CTL = 1
D_GPIOs
Allowed
D_GPIO[3:0]
D_GPIO[3:0]
D_GPIO[1:0]
D_GPIO0
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