DS90UH940-Q1 Datasheet, PDF (24/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
8 Detailed Description
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8.1 Overview
The DS90UH940-Q1 receives a 35-bit symbol over single or dual serial FPD-Link III pairs operating at up to 3.36
Gbps line rate in 1-lane FPD-Link III mode and 2.975 Gbps per lane in 2-lane FPD-Link III mode. The
DS90UH940-Q1 converts this stream into a CSI-2 MIPI Interface (4 data channels + 1 clock, or 8 data channels
+ 2 clocks in replicate mode). The FPD-Link III serial stream contains an embedded clock, video control signals,
audio, GPIOs, I2C, and the DC-balanced video data and audio data which enhance signal quality to support AC
coupling.
The DS90UH940-Q1 is intended for use with the DS90UH949-Q1 or DS90UH947-Q1 Serializers, but is also
backward compatible to the DS90UH925Q-Q1, DS90UH925AQ-Q1, and DS90UH927Q-Q1 FPD-Link III
Serializers.
The DS90UH940-Q1 deserializer attains lock to a data stream without the use of a separate reference clock
source, which greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the
serializer regardless of the data pattern, delivering true automatic “plug and lock” performance. It can lock to the
incoming serial stream without the need of special training patterns or sync characters. The deserializer recovers
the clock and data by extracting the embedded clock information, validating then deserializing the incoming data
stream. It also applies decryption through a High-Bandwidth Digital Content Protection (HDCP) Cipher to this
video and audio data stream following reception of the data from the FPD-Link III decoder. On-chip non-volatile
memory stores the HDCP keys. All key exchange is done through the FPD-Link III bidirectional control interface.
The decrypted MIPI CSI-2 interface is provided to the processor.
The DS90UH940-Q1 deserializer incorporates an I2C compatible interface. The I2C compatible interface allows
programming of serializer or deserializer devices from a local host controller. In addition, the devices incorporate
a bidirectional control channel (BCC) that allows communication between serializer/deserializer as well as remote
I2C slave devices.
The bidirectional control channel (BCC) is implemented via embedded signaling in the high-speed forward
channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to
serializer). Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial
link from one I2C bus to another. The implementation allows for arbitration with other I2C compatible masters at
either side of the serial link.
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