DS90UH940-Q1 Datasheet, PDF (13/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

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DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
7.7 AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN TYP
GPIO BIT RATE
R_b,FC
Forward Channel Bit Rate
PCLK = 25MHz - 170MHz⁽¹⁾
GPIO[3:0]
0.25 *
PCLK
R_b,BC
Back Channel Bit Rate
133
R_b,BC
Back Channel Bit Rate
High Speed (2-lane Mode), 1
D_GPIO[3:0]
D_GPIO active.
2.0
See Table 4.
High Speed (2-lane Mode), 2
D_GPIO's active.
1.33
See Table 4.
High Speed (2-lane Mode), 4
D_GPIO's active.
800
See Table 4.
Normal mode. See Table 4.
133
t_GPIO,FC
GPIO Pulse Width, Forward
Channel
GPIO[3:0]
>2 /
PCLK ⁽¹⁾
t_GPIO,BC
RESET
GPIO Pulse Width, Back Channel
GPIO[3:0]
20
t_LRST
PDB Reset Low Pulse
LOOP-THROUGH MONITOR OUTPUT
PDB
2
E_W
Differential Output Eye Opening
Width
E_H
Differential Output Eye Height
FPD-LINK III CML INPUT
RL = 100Ω, Jitter frequency >
PCLK⁽¹⁾ / 40
See Figure 2.
CMLOUTP,
CMLOUTN
0.4
>300
t_DDLT
Lock Time
See Figure 4.
RIN0+,
RIN0-,
RIN1+,
5
RIN1-
I2S TRANSMITTER
t_J,I2S
t_I2S
t_HC,I2S
t_LC,I2S
t_SR,I2S
t_HR,I2S
Clock Output Jitter
I2S Clock Period⁽³⁾
I2S Clock High Time⁽³⁾
I2S Clock Low Time⁽³⁾
I2S Set-up Time
I2S Hold Time
See Figure 9.
See Figure 9.
See Figure 9.
See Figure 9.
See Figure 9.
I2S_CLK
I2S_DA,
I2S_DB,
I2S_DC,
I2S_DD
2
>2 /
PCLK ⁽¹⁾
or >77
0.48
0.48
0.4
0.4
MAX UNIT
Mbps
kbps
Mbps
Mbps
kbps
kbps
s
μs
ms
UI
mV
10⁽²⁾ ms
ns
ns
t_I2S
t_I2S
t_I2S
t_I2S
(1) PCLK refers to the equivalent pixel clock frequency, which is equal to the FPD-Link III line rate / 35.
(2) This parameter is specified by characterization and is not tested in production.
(3) I2S specifications for t_LC,I2S and t_HC,I2S pulses must each be greater than 1 PCLK period to ensure sampling and supersedes the
0.35*t_I2S requirement. t_LC,I2S and t_HC,I2S must be longer than the greater of either 0.35*t_I2S or 2 * PCLK.
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