DS90UH940-Q1 Datasheet, PDF (18/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
Timing Diagrams and Test Circuits (continued)
PDB
VIH(min)
RIN[1:0]±
LOCK
t_DDLT
TRI-STATE
Figure 4. CML PLL Lock Time
RIN[1:0]+
VTL
VCM
VTH
RIN[1:0]-
VOH(min)
GND
Figure 5. FPD-Link III Receiver DC V_TH/V_TL Definition
I2S_CLK,
MCLK
I2S_WC,
I2S_D[D:A]
V_OHmin
V_OLmax
t_ROS
1/2 V_DDIO
t_ROH
V_DDIO
GND
V_DDIO
GND
Figure 6. Output Data Valid (Setup and Hold) Times
BISTEN
PASS
(w/errors)
Prior BIST Result
Current BIST Test - Toggle on Error
1/2 V_DDIO
t_PASS
1/2 V_DDIO
Result Held
Figure 7. BIST PASS Waveform
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SDA
t_f
SCL
START
t_LOW
t_r
t_f
t_HD;STA
t_BUF
t_r
t_HD;STA
t_HD;DAT
t_HIGH
t_SU;DAT
t_SU;STA
t_SU;STO
REPEATED
START
STOP START
Figure 8. Serial Control Bus Timing Diagram
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