DS90UH940-Q1 Datasheet, PDF (41/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

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DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
8.4.3 CSI-2 Interface
The DS90UH940-Q1 (in default mode) takes RGB 24-bpp data bits defined in the serializer and directly maps to
the pixel color space in the data frame. The DS90UH940-Q1 follows the general frame format as described per
the CSI-2 standard (Figure 29). Upon the end of the vertical sync pulse (VS), the DS90UH940-Q1 generates the
Frame End and Frame Start synchronization packets within the vertical blanking period. The timing of the Frame
Start will not reflect the timing of the VS signal.
Upon the rising edge of the DE signal, each active line is output in a long data packet with the defined data
format (Figure 13). At the end of each packet, the data lanes Dn± return to the LP-11 state, while the clock lane
CLK± continue outputting the high speed clock.
The DS90UH940-Q1 CSI-2 transmitter consists of a high speed clock (CLK±) and data (Dn±) outputs based on a
source synchronous interface. The half rate clock at CLK± is derived from the pixel clock sourced by the
clock/data recovery circuit of the DS90UH940-Q1. The CSI-2 clock frequency is 3.5 times (4 MIPI lanes) or 7
times (2 MIPI lanes) the recovered pixel clock frequency. The MIPI DPHY outputs either 2 or 4 high speed data
lanes (Dn±) according to the CSI-2 protocol. The data rate of each lane is 7 times (4 MIPI lanes) or 14 times (2
MIPI lanes) the pixel clock. As an example in a 4 MIPI lane configuration, at a pixel clock of 150 MHz, the CLK±
runs at 525 MHz, and each data lane runs at 1050 Mbps.
The half-rate clock maintains a quadrature phase relationship to the data signals and allows receiver to sample
data at the rising and falling edges of the clock (DDR). Figure 10 shows the timing relationship of the clock and
data lines. The DS90UH940-Q1 supports continuous high speed clock. High speed data are sent out at data
lanes Dn± in bursts. In between data bursts, the data lanes return to Low Power (LP) States in according to
protocol defined in D-PHY standard. The rising edge of the differential clock (CSI_CLK+ – CSI_CLK-) is sent
during the first payload bit of a transmission burst in the data lanes.
Frame Blanking
FS
Line Blanking
Line Data
FE
(1 to N) t_LPX ^{Frame Blanking}
FS
Line Blanking
Line Data
FE
Frame Blanking
Figure 29. CSI-2 General Frame Format
8.4.4 Input Display Timing
The DS90UH940-Q1 has built−in support to detect the incoming video format extracted from the FPD-Link III
datastream(s) and automatically generate CSI-2 output timing parameters accordingly. The input video format
detection is derived from progressive display resolutions based on the CEA−861D specification. The video data
rate and frame rate is determined by measuring internal VS and DE signals.
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