DS90UH940-Q1 Datasheet, PDF (45/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

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DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 34 and a WRITE is shown in Figure 35.
Slave Address
Register Address
S
A
2
A
1
A
0
a
0
c
k
a
c
k
Sr
Slave Address
a
AA
21
A
0
1
c
k
Data
a
c
k
P
Figure 34. Serial Control Bus — READ
Slave Address
Register Address
S
A
2
A
1
A
0
a
0
c
k
a
c
k
Data
a
c
k
P
Figure 35. Serial Control Bus — WRITE
The I2C Master located at the Deserializer must support I2C clock stretching. For more information on I2C
interface requirements and throughput considerations, please refer to TI Application Note SNLA131.
8.5.2 Multi-Master Arbitration Support
The Bidirectional Control Channel in the FPD-Link III devices implements I2C compatible bus arbitration in the
proxy I2C master implementation. When sending a data bit, each I2C master senses the value on the SDA line.
If the master is sending a logic 1 but senses a logic 0, the master has lost arbitration. It will stop driving SDA,
retrying the transaction when the bus becomes idle. Thus, multiple I2C masters may be implemented in the
system.
For example, there might also be a local I2C master at each camera. The local I2C master could access the
Image Sensor and EEPROM. The only restriction would be that the remote I2C master at the camera should not
attempt to access a remote slave through the BCC that is located at the host controller side of the link. In other
words, the control channel should only operate in camera mode for accessing remote slave devices to avoid
issues with arbitration across the link. The remote I2C master should also not attempt to access the deserializer
registers to avoid a conflict in register access with the Host controller.
If the system does require master-slave operation in both directions across the BCC, some method of
communication must be used to ensure only one direction of operation occurs at any time. The communication
method could include using available read/write registers in the deserializer to allow masters to communicate
with each other to pass control between the two masters. An example would be to use register 0x18 or 0x19 in
the deserializer as a mailbox register to pass control of the channel from one master to another.
8.5.3 I2C Restrictions on Multi-Master Operation
The I2C specification does not provide for arbitration between masters under certain conditions. The system
should make sure the following conditions cannot occur to prevent undefined conditions on the I2C bus:
• One master generates a repeated Start while another master is sending a data bit.
• One master generates a Stop while another master is sending a data bit.
• One master generates a repeated Start while another master sends a Stop.
Note that these restrictions mainly apply to accessing the same register offsets within a specific I2C slave.
8.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
When using the latest generation of FPD-Link III devices (DS90UH94x-Q1), serializers or deserializer registers
may be accessed simultaneously from both local and remote I2C masters. These devices have internal logic to
properly arbitrate between sources to allow proper read and write access without risk of corruption.
Access to remote I2C slaves would still be allowed in only one direction at a time (Camera or Display mode).
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