DS90UH940-Q1 Datasheet, PDF (1/87 Pages) Texas Instruments – FPD-Link III to CSI-2 Deserializer

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DS90UH940-Q1
SNLS478A – NOVEMBER 2014 – REVISED JANUARY 2016
DS90UH940-Q1 1080p FPD-Link III to CSI-2 Deserializer with HDCP
1 Features
•1 Supports Pixel Clock Frequency up to 170 MHz
for WUXGA (1920x1200) and 1080p60
Resolutions with 24-bit Color Depth
• 1-lane or 2-lane FPD-Link III Interface with De-
skew Capability
• MIPI D-PHY / CSI-2 Transmitter
– CSI-2 Output Ports with selectable 2- or 4-lane
operation
– Supports up to 4 Data Lanes per CSI-2 port,
Each Lane up to 1.3 Gbps
– Video formats: RGB888/666/565,
YUV422/420, RAW8/10/12
– Programmable Virtual Channel Identifier
• Integrated HDCP cipher engine with on-chip key
storage
• High Speed GPIO up to 2.0 Mbps
• Supports up to 15 meters of cable with automatic
temperature and aging compensation
• SPI Control Interfaces up to 3.3 Mbps
• I²C (Master/Slave) with 1 Mbps Fast-mode Plus
• Adaptive Receive Equalization
• Supports 7.1 Multiple I2S (4 data) Channels
• Backward Compatible to DS90UH925/925AQ-Q1
and DS90UH927Q-Q1 FPD-Link III Serializers
• Automotive Grade Product: AEC-Q100 Grade 2
Qualified
2 Applications
• Automotive Infotainment:
– Central Information Displays
– Rear Seat Entertainment Systems
– Digital Instrument Clusters
• ADAS Camera Systems
3 Description
The DS90UH940-Q1 is a FPD-Link III Deserializer
which, in conjunction with the DS90UH949/947/929-
Q1 Serializers, converts 1-lane or 2-lane FPD-Link III
streams into a MIPI CSI-2 interface. The Deserializer
is capable of operating over cost-effective 50Ω single-
ended coaxial or 100Ω differential shielded twisted-
pair (STP) cables. It recovers the data from one or
two FPD-Link III serial streams and translates it into a
Camera Serial Interface (CSI-2) format supporting
video resolutions up to WUXGA and 1080p60 with
24-bit color depth.
The FPD-Link III interface supports video and audio
data transmission and full duplex control, including
I²C and SPI communication, over the same
differential link. Consolidation of video data and
control over two differential pairs reduces the
interconnect size and weight and simplifies system
design. EMI is minimized by the use of low voltage
differential signaling, data scrambling, and
randomization. In backward compatible mode, the
device supports up to WXGA and 720p resolutions
with 24-bit color depth over a single differential link.
The device automatically detects the FPD-Link III
channels and provides a clock alignment and de-
skew functionality without the need for any special
training patterns. This ensures skew phase tolerance
from mismatches in interconnect wires such as PCB
trace routing, cable pair-to-pair length differences,
and connector imbalances.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90UH940-Q1
WQFN NKD (64) 9.00 mm x 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Applications Diagram
HDMI
or
DP++
VDDIO
(3.3V / 1.8V)
1.8V 1.1V
Mobile
Device
or
Graphics
Processor
IN_CLK-/+
IN_D0-/+
IN_D1-/+
IN_D2-/+
CEC
DDC
HPD
DOUT0+
DOUT0-
DOUT1+
DOUT1-
DS90UH949-Q1
Serializer
I2C
IDx
HS_GPIO
(SPI)
1
FPD-Link III
2 lanes
I2C
IDx
HS_GPIO
(SPI)
3.3V 1.2V
VDDIO
(3.3V / 1.8V)
RIN0+
RIN0-
RIN1+
RIN1-
DS90UH940-Q1
Deserializer
MIPI CSI-2
D3+/-
D2+/-
D1+/-
D0+/-
CLK+/-
Application
Processor
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.