LM98640QML-SP Datasheet, PDF (47/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

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8.2 Typical Application
8.2.1 Sample/Hold Mode
0.1 2F
0.1 2F
0.1 2F
VA
CCD Sensor
and
Output Signal
Buffers
0.1 2F
0.1 2F
0.1 2F
VCOM1
VDD33
VDD33
VSS33
VSS33
OS1-
OS1+
VSS33
VCLP
VSS33
OS2+
OS2-
VSS33
VSS33
VDD33
VDD33
VCOM2
VA
10 kÖ
LM98640
LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
100Ö
VD
ATB0
VDD18
VSS18
TXCLK-
TXCLK+
TXOUT0-
TXOUT0+
TXOUT1-
TXOUT1+
TXOUT2-
TXOUT2+
TXOUT3-
TXOUT3+
TXFRM-
TXFRM+
VD
VSS18
VDD18
Image Processor/
ASIC
VA
0.1 2F
0.1 2F
0.1 2F
Serial Interface and
Device Control Bus
CCD Clock Drivers
CCD Timing Output Bus
3.3V
Pin 65 Pins 2,3 Pins 15,16 Pin 22
VREFBG VA
VA
VA
Pin 23
VA
Pin 60
VA
Pin 61
VA
Pin 32 Pin 35 Pin 50 Pins 53,54
VD
VD
VD
VD
0.1 2F 0.1 2F
0.1 2F
0.1 2F
0.1 2F
0.1 2F
0.1 2F
0.1 2F 0.1 2F 0.1 2F 0.1 2F
VA
1.8V
+ _{4.7 2F}
VD
+
4.7 2F
Pins 4,5 Pins 13,14 Pin 21
Pin 24
Pin 59
Pin 62
Pin 31 Pin 36 Pin 49 Pins 55,56
Figure 29. Typical CDS Mode Application Diagram
8.3 Initialization Set Up
1. Power up supply voltages VDD33 and VDD18
2. Apply signal to INCLK
3. Write all configuration registers. Be sure to set the INCLK Range (2x05) and Sample & Hold (0x06) for the
INCLK frequency used.
4. Write the Test & Scan register (3x0D) before the Clock Monitor register (0x09).
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