LM98640QML-SP Datasheet, PDF (44/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
www.ti.com
ADDRESS
(BINARY)
11 0000
11 0001
11 0010
11 0011
11 0100
11 0101
11 0110
11 0111
11 1000
Table 9. Register Definitions - Digital Configuration
REGISTER
TITLE
Test Pattern Start
Test Pattern Start
Test Pattern Width
Test Pattern Width
Test Pattern Control
BASELINE
(BINARY)
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
BIT(s)
DESCRIPTION
[15:8]
[7:0]
[15:8]
[7:0]
[7:0]
Upper 8 bits of the Test Pattern start value. Specifies the number of
pixels after the leading edge of CLPIN to the Valid Pixel region.
Lower 8 bits of the Test Pattern start value. Specifies the number of
pixels after the leading edge of CLPIN to the Valid Pixel region.
Upper 8 bits of the Test Pattern Width value. Specifies, in number of
pixels, the width of the Valid Pixel region.
Lower 8 bits of the Test Pattern Width value. Specifies, in number of
pixels, the width of the Valid Pixel region.
Test Pattern Control Register.
[7] Programmable Pattern Switch
0 Disabled. Normal LVDS output operation.
1 Enabled. AFE outputs LVDS test patterns.
[6:4] Test Pattern Mode
000 Fixed Code
001 Horizontal Gradient Scan (Main Scan)
010 Vertical Gradient Scan (Sub Scan)
011 Grid Scan (Lattice Pattern)
100 Strip Pattern
101 LVDS Test Pattern. (Synchronous to CLPIN)
110 LVDS Test Pattern. (Asynchronous)
111 Not Used.
[3] Pseudo Random Pattern Enable.
Overrides Programmable Patter Switch setting (bit 7). Normally only
one should be on.
[2] Load Seed Enable.
When set, the seed value in the Test Pattern Value Register is loaded
in the LFSR at the leading edge of CLPIN.
Test Pattern Pitch
0000 0000
Test Pattern Step
0000 0000
Test Pattern Channel 0000 0000
Offset
[1:0] Test Pattern Output Channel Select.
00 Both Channels
01 Channel 1
10 Channel 2
11 Not Used
[7:0] Test Pattern pitch, specifies number of pixels for H Gradient pattern
and Stripe pattern, or number of lines in the V Gradient pattern, or
specifies pixels & lines in the Lattice pattern.
[7:0] Test Pattern Step Code. Specifies step size in LSB codes the pattern is
incremented in H Gradient and V Gradient pattern. In Lattice and Stripe
pattern it specifies the code during the lower step.
[7:0] Test Pattern Channel Offset Register.
[7:4] Not Used.
Test Pattern Value
0000 0000
[3:0]
[15:8]
Test Pattern Channel Offset. This specifies the number of lines the
pattern on Channel 2 is delayed from Channel 1. This offset is
maintained throughout the pattern.
Upper 8 bits of Test Pattern Value Register. Specifies the upper 8 bits
of the test value code during Fixed Pattern and LVDS test, initial value
during H Gradient & V Gradient pattern, and higher value in the Lattice
and Stripe Pattern.
44
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LM98640QML-SP