LM98640QML-SP Datasheet, PDF (39/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

www.ti.com
ADDRESS
(BINARY)
00 0001
00 0010
LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
Table 6. Register Definitions - Analog Configuration (continued)
REGISTER
TITLE
Powerdown Control
BASELINE
(BINARY)
0000 0000
BIT(s)
DESCRIPTION
[7:0] Powerdown Control Register
[7] Master Powerdown
0 Fully Powered.
1 Powerdown Mode. Over rides bits [6:0].
[6] VCLP Powerdown
0 VCLP Fully Powered.
1 VCLP Powerdown Mode.
[5] Channel 2 Reference Buffer Powerdown
0 Reference Buffer Fully Powered.
1 Reference Buffer Powerdown Mode.
[4] Channel 1 Reference Buffer Powerdown
0 Reference Buffer Fully Powered.
1 Reference Buffer Powerdown Mode.
[3] Channel 2 PGA Powerdown
0 OpAmp Fully Powered.
1 OpAmp Powerdown Mode.
[2] Channel 1 PGA Powerdown
0 OpAmp Fully Powered.
1 OpAmp Powerdown Mode.
[1] Channel 2 ADC Powerdown
0 Amplifier Fully Powered.
1 Amplifier Powerdown Mode.
PGA Power Trimming 0010 0100
[0] Channel 1 ADC Powerdown
0 ADC Fully Powered.
1 ADC Powerdown Mode.
[7:0] PGA Power Trimming Register.
[7:6] Not Used
[5:3] PGA Stage 1 Current Trimming
Tunable between 000-Weak to 111-Strong (Default 100)
[2:0] PGA Stage 2 Current Trimming
Tunable between 000-Weak to 111-Strong (Default 100)
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LM98640QML-SP
Submit Documentation Feedback
39