LM98640QML-SP Datasheet, PDF (33/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

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LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
Each pattern consists of a Start Period and Valid Pixel region. During the Start Period the output is the minimum
code (0x0000). The Valid Pixel region contains the selected Test Pattern Mode output. The length (in pixels) of
the Start period is set using the Test Pattern Start register, and the width of the Valid Pixel region is set using the
Test Pattern Width register.
To start the test pattern generation, enable Test Mode using bit[1] of the Test and Scan Register (0x3D). Then
load all parameters for the desired test pattern into the registers, and set Pattern Enable bit of the Test Pattern
Control Register (0x34). Changing pattern parameters after the Pattern Enable bit is set may result in undesired
output. The pattern will start at the next leading edge of CLPIN.
7.4.2.1 Test Mode 0 - Fixed Pattern
This test mode provides an LVDS output with a fixed value output during the valid pixel region. The fixed value is
set via the Test Pattern Value registers. The Test Pattern Value register is split into two registers the upper 6 bits
of the test code in first register, and the lower 8 bits of the test code in the second.
7.4.2.2 Test Mode 1 - Horizontal Gradient
This mode provides LVDS data that progresses horizontally from dark to light output values. This mode is highly
variable, allowing control over the starting value of the gradient, the width of the gradient, and the increment rate
of the gradient. The starting value can be set in the Test Pattern Value register, the width (in number of pixels) of
each gradient step is set via Test Pattern Pitch register, and increment rate (in LSBs) is set via the Test Pattern
Step register. When the LVDS Horizontal Gradient test pattern is selected, the ramp begins immediately and
counts to the maximum value, and then repeats throughout the entire Valid Pixel region.
7.4.2.3 Test Mode 2 - Vertical Gradient
This mode is similar to the Horizontal Gradient, only the gradient is in the vertical direction. See the Horizontal
Gradient mode description for details.
7.4.2.4 Test Mode 3 - Lattice Pattern
This mode provides LVDS data that creates a lattice grid. The lattice is made of dark lines on a light background.
The line output value is set by Test Pattern Step register, and background value is set by Test Pattern Value
register. The number of pixels & lines in the lattice is set via Test Pattern Pitch register.
7.4.2.5 Test Mode 4 - Stripe Pattern
This mode provides LVDS data that creates a vertical stripe pattern. The stripe pattern is made of dark and light
lines. The output value of the dark portion is set via Test Pattern Step register, and the light portion is set via
Test Pattern Value register. The stripe width in pixels is set via Test Pattern Pitch register.
7.4.2.6 Test Mode 5 - LVDS Test Pattern (Synchronous)
This mode provides an LVDS output with a fixed value repeated continuously. The pattern starts at the leading
edge of CLPIN. The fixed value is set via the Test Pattern Value registers. The Test Pattern Value register is split
into two registers the upper 8 bits of the test code in first register, and the lower 8 bits of the test code in the
second. This is useful for system debugging of the LVDS link and receiver circuitry.
7.4.2.7 Test Mode 6 - LVDS Test Pattern (Asynchronous)
This mode provides an LVDS output with a fixed value repeated continuously. The pattern starts asynchronously
without CLPIN. The fixed value is set via the Test Pattern Value registers. The Test Pattern Value register is split
into two registers the upper 8 bits of the test code in first register, and the lower 8 bits of the test code in the
second. This is useful for system debugging of the LVDS link and receiver circuitry.
7.4.2.8 Pseudo Random Number Mode
This mode provides LVDS data produced from the following polynomial:
P(x) = X¹⁴ + X¹³ + X¹¹ + X⁹ + 1
To start the Pseudo Random Number mode, set the Test Mode bit of the Test and Scan Register. Then load the
seed value in the Test Pattern Value register, and set the Pseudo Random Enable bit of the Test Pattern Control
register. The pattern will start outputting after the next leading edge of CLPIN.
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