LM98640QML-SP Datasheet, PDF (30/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
www.ti.com
7.3.5 Analog to Digital Converter
The LM98640QML has a 14bit Analog to Digital Converts (ADC) for each channel. Each ADC has maximum and
minimum conversion rate of 40 MSPS and 5 MSPS per channel respectively. The DNL performance is +/-0.5LSB
and +/-2LSB for INL for a 14bit out. The noise floor is -79dB at 2V with a programmable gain of 0dB. If an out of
range pixel is presented to the ADC, the ADC will return to full compliance within two cycles of the pixel clock.
7.3.6 LVDS Output
7.3.6.1 LVDS Output Voltage
The LM98640QML output data is presented in LVDS format. Table 3 shows the available LVDS differential
output voltage (VOD) settings and its associated offset voltage (VOS).
Table 3. LVDS Differential Output Voltage Settings
VOD
250 mV
300 mV
350 mV
400 mV
VOS
1.2 V
1.2 V
1.1 V
1.1 V
7.3.6.2 LVDS Output Modes
The LM98640QML has a unique serial LVDS output format to protect data transfer during DLL upsets. The
format provides a buffer on either side of the data word, this is accomplished by clocking a 14bit word using a
16bit clock rate. In the event of an upset that affects the DLL the output clock period could fluctuate; with no
buffer for the data word this fluctuation could cause the loss of one or more of the data word bits, but because
the LM98640QML provides the buffer the fluctuation does not cause any data loss. The data can also be sent
out in two modes: Dual or Quad Lane. The following sections describe these two modes.
7.3.6.3 TXFRM Output
The LM98640QML output includes a frame signal (TXFRM) that should be used to locate the beginning and end
of a particular pixel's serial data word. The rising edge of TXFRM is coincident with the pixel's leading bit
transition (TXOUT MSB). This TXFRM rising edge can be detected by the capturing FPGA or ASIC to mark the
start of the serial data word.
In CDS mode, the input sampling amplifier has two physical paths through which a particular pixel will be
sampled. These two sampling paths are a requirement in the Correlated Double Sampling architecture. The
sampling of the one pixel will travel the first path (arbitrarily called an even pixel), and the sampling of the next
pixel will travel the second path (called an odd pixel). The sampling will continue in an even/odd/even/odd
fashion for all pixels processed in a particular channel. Due to slight variances in the sampling paths (most
commonly a difference in switched capacitor matching), the processing of identical pixels through the two
different paths may result in a small offset in ADC output data between the two paths. To correct this, a simple
digital offset can be applied in post processing to either the even pixel data or the odd pixel data. To simplify this
action, the LM98640QML will indicate (with the TXFRM signal) whether the pixel traveled the even path or the
odd path. For all "Odd" pixels, the TXFRM signal is high for three TXCLK periods. For "Even" pixels, the TXFRM
signal is high for two TXCLK periods. In Sample and Hold Mode there is only one sampling path, therefore there
is no need to indicate an even or odd pixel. As a result, the TXFRM signal is the same for every pixel in Sample
and Hold mode (i.e. high for three TXCLK periods).
7.3.6.3.1 Output Mode 1 - Dual Lane
In Dual Lane mode each input channel has its own data output presented at 16X the pixel clock rate. A frame
signal (TXFRM) is output at the pixel clock rate with the rising edge occurring coincident with the transition of the
MSB of the data. In Sample/Hold Modes of operation, the falling edge is coincident with the transition of bit 7 of
the data. In CDS Mode, the falling edge of TXFRM toggles between the transition of bit 9 and bit 7 of the data. A
differential clock is also output with transitions aligned with the center of the data eye. Data rates for Dual Lane
mode range from 80Mbps, with a 5 MHz clock, up to 640 Mbps, with a 40 MHz clock.
30
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LM98640QML-SP