LM98640QML-SP Datasheet, PDF (36/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
www.ti.com
7.6 Register Maps
Registers need to be written with baseline values after power-up to place part in a valid state.
Table 5. Configuration Registers
ADDRE
SS
(BINAR
Y)
REGISTER TITLE
(MNEMONIC)
ANALOG CONFIGURATION
BASELINE
(BINARY)
00 0000
Main
Configuration
0000 0100
00 0001
00 0010
00 0011
Powerdown
Control
PGA Power
Trimming
ADC Power
Trimming
0000 0000
0010 0100
0101 1011
00 0100 VCLP Control 0111 0100
00 0101
LVDS Output
Modes
0000 1110
00 0110 Sample & Hold 1000 0001
00 0111
Status
0000 0000
00 1000
Reserved
0000 0000
00 1001 Clock Monitor 0000 0000
00 1010
Reserved
0000 0000
00 1011
Reserved
0000 0000
00 1100
Reserved
0000 0000
00 1101
Reserved
0000 0000
00 1110
Reserved
0000 0000
00 1111
Reserved
0000 0000
GAIN & OFFSET DAC CONFIGURATION
01 0000
CDAC1
0000 0000
01 0001
CDAC1
1111 1111
01 0010
FDAC1
0000 0000
01 0011
FDAC1
1111 1111
01 0100
Reserved
0000 0000
01 0101
PGA1
0110 0001
01 0110
Reserved
0000 0000
01 0111
Reserved
0000 0000
01 1000
CDAC2
0000 0000
01 1001
CDAC2
1111 1111
01 1010
FDAC2
0000 0000
01 1011
FDAC2
1111 1111
01 1100
PGA2
0110 0001
01 1101
Reserved
0000 0000
01 1110
Reserved
0000 0000
01 1111
Reserved
0000 0000
TIMING CONFIGURATION
10 0000
Clamp Start
0000 1000
10 0001
Clamp End
0001 1100
10 0010 Sample Start 0010 1000
10 0011
Sample End
0011 1100
10 0100
Reserved
0011 0100
10 0101 INCLK Range 0000 0010
Bit 7
Bit 6
REGISTER and BIT DESCRIPTION
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Not Used
Master
Powerdown
Coarse
Fine DAC
DAC Enable Enable
Reserved
VCLP Ch2 Ref Buf Ch1 Ref Buf
Powerdown Powerdown Powerdown
CLPIN
Gating
Enable
Ch2 PGA
Powerdown
CDS Gain
Enable
Ch1 PGA
Powerdown
Reserved
Ch2 ADC
Powerdown
CDS Enable
Ch1 ADC
Powerdown
Reserved
PGA Stage 2 Bias Current Trimming
PGA Stage 1 Bias Current Trimming
Reserved
Not Used
Buffer
Enable
Clear
Reserved
S/H Enable
Not Used
ADC Current Trimming 2
ADC Current Trimming 1
VCLP
Enable
VCLP Voltage Level
Reserved
Reserved
Quad Lane
Enable
LVDS
Enable
LVDS Control
Not Used
Ref Buf Power Level
Reserved
Not Used
False Lock
Reserved
Enable/Select
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Offset Value bits 7:0
Not Used
Offset Value bits 7:0
Not Used
PGA Gain Value
Not Used
Not Used
Not Used
Offset Value bits 7:0
Not Used
Offset Value bits 7:0
PGA Gain Value
Not Used
Not Used
Not Used
Offset bit 8
Offset bit 8
Offset Bit 8
Offset Bit 8
Not Used
Not Used
Not Used
Not Used
Not Used
INCLK Range
Clamp Start Index
Clamp End Index
Sample Start Index
Sample End Index
Reserved
Not Used
Reserved
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