LM98640QML-SP Datasheet, PDF (34/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
7.5 Programming
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7.5.1 Serial Interface
A serial interface is used to write and read the configuration registers. The interface is a four wire interface using
SCLK, SEN, SDI, and SDO connections. The serial interface clock (SCLK) must be less than the main input
clock (INCLK) for INCLK speeds of less than 20MHz, for INCLK speeds greater than 20MHz SCLK must remain
below 20MHz. The main input clock (INCLK) to the LM98640QML must be active during all Serial Interface
commands. The Serial Interface pins are high impedance while SEN is high, this allows multiple slave devices to
be used with a single master device.
After power-up, all configuration registers must be written, using the serial interface, to place the part in a valid
state.
Default registers must be written to the baseline values.
Be sure to set the INCLK Range (2x05) and Sample & Hold (0x06) registers for the sample rate being used.
Write the Clock Monitor (0x09) register after the Test & Scan Control (3x0D) register.
7.5.2 Writing to the Serial Registers
To write to the serial registers using the four wire interface, the timing diagram shown in Figure 26 must be met.
First, SEN is toggled low. At the rising edge of the first clock, the master should assume control of the SDI pin
and begin issuing the write command. The write command is built of a "write" bit (0), device address bit (0), six
bit register address, and eight bit register value to be written. SDI is clocked into the LM98640QML at the rising
edge of SCLK. The LM98640QML assumes control of the SDO pin during the first eight clocks of the cycle.
During this period, data is clocked out of the device at the rising edge of SCLK. The eight bit value clocked out is
the contents of the previously addressed register, regardless if the previous command was a read or a write.
When SEN toggles high, the register is written to, and the LM98640QML now functions with this new data.
7.5.3 Reading the Serial Registers
To read to the serial registers using the four wire interface, the timing diagram shown in Figure 27 must be met.
Reading the registers takes two cycles. To start the first cycle, SEN is toggled low. At the rising edge of the first
clock, the master should assume control of the SDI pin and begin issuing the read command. The read
command is built of a "read" bit (1), device address bit (0), six bit register address, and eight "don't care" bits.
SDI is clocked into the LM98640QML at the rising edge of SCLK. SEN is toggled high for a delay of at least
t_SENW (see Figure 28). The second cycle begins when SEN is toggled low. The LM98640QML assumes control of
the SDO pin during the first eight clocks of the cycle. During this period, data is clocked out of the device at the
rising edge of SCLK. The eight bit value clocked out is the contents of the previously addressed register. The
next command can be sent on the SDI pin simultaneously during this second cycle. When SEN toggles high, the
register is not written to, but its contents are staged to be outputted at the beginning of the next command.
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