LM98640QML-SP Datasheet, PDF (41/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

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ADDRESS
(BINARY)
00 0110
00 0111
00 1001
LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
Table 6. Register Definitions - Analog Configuration (continued)
REGISTER
TITLE
Sample & Hold
BASELINE
(BINARY)
1000 0001
BIT(s)
DESCRIPTION
[7:0] Sample & Hold Mode Register
[7] Sample & Hold Mode Enable
0 Disabled.
1 Enabled.
[6:3] Not Used.
Status
0000 0000
[2:1]
[0]
[7:0]
Reference Buffer Power Level
11 100% Power. Used for F_INCLK = 20-40MHz.
10 60% Power. Used for F_INCLK = 10-20MHz.
01 60% Power. Used for F_INCLK = 10-20MHz.
00 30% Power. Used for F_INCLK = 5-10MHz.
Reserved.
Status Register. (Read Only)
[7:1] Not Used.
Clock Monitor
0000 0000
[0] False Lock Detect.
Indicates if DLL is locked into a half frequency state.
[7:0] Internal Clock Signal Monitor Register
[7:5] Not Used.
[4:3] Enable and select clocks to be monitored on the Digital Timing
Monitor. (DTM)
00 Disable Digital Timing Monitor Pins (DTM0, DTM1)
01 Send CLAMP_EVEN to DTM0 pin, and SAMPLE_EVEN to DTM1
10 Send CLAMP_ODD to DTM0 pin, and SAMPLE_ODD to DTM1
11 Send ODD tag and ADC Clock to the DTM.
[2:0] Reserved. Set to 000.
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