LM98640QML-SP Datasheet, PDF (32/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
www.ti.com
7.3.7 Clock Receiver
A differential clock receiver is used to generate all clock signals on the LM98640QML. The clock input should be
externally terminated with 100 Ohms between the input clock pins. The clock may be DC or AC coupled to the
AFE.
7.3.8 Power Trimming
The LM98640QML provides an adaptive power scaling feature that allows the user to optimize power
consumption based on the maximum operating frequency and the maximum amount of gain required. The power
scaling mode is selectable through the PGA Power Trimming and ADC Power Trimming registers (0x02,0x03).
The settings in these registers are common for both channels PGA and ADC. Using these registers the user can
control the current of the two stages of the PGA, and the current for the two levels of the ADC. The following
table provides a set of baseline configurations for various operating frequencies and gain ranges.
These configurations should be treated as baseline values and can be tuned to your specific application.
OPERATING FREQUENCY
1-4x MAX PGA GAIN
5 - 15 MSPS
PGA Power Trimming = 0x00
ADC Power Trimming = 0x00
15 - 25 MSPS
PGA Power Trimming = 0x01
ADC Power Trimming = 0x00
25 - 40 MSPS
PGA Power Trimming = 0x01
ADC Power Trimming = 0x08
1-8x MAX PGA GAIN
PGA Power Trimming = 0x01
ADC Power Trimming = 0x00
PGA Power Trimming = 0x09
ADC Power Trimming = 0x00
PGA Power Trimming = 0x09
ADC Power Trimming = 0x08
7.4 Device Functional Mode
7.4.1 Powerdown Modes
The LM98640QML provides several ways to save power when the device is not in normal usage mode. Using
the Powerdown Control Register (0x01) the part can be placed into Powerdown Mode, or Single Channel Mode.
In Powerdown Mode (Powerdown Control, bit[7]) the following blocks are placed in a Powerdown mode: VCLP,
Channel 1 & 2 Reference Buffers, Channel 1 & 2 PGA OpAmps, and Channel 1 & 2 Amplifiers. Powerdown
Mode will override all other Powerdown Control Register bits. To place the part in Single Channel Mode each
block of the unused channel can be powered down using their respective control bits (Powerdown Control,
bits[5:0]). If an external reference clamp is used the VCLP block can be powered down during any Power mode.
For applications operating at a low enough frequency additional power can be saved by powering down one
channel reference buffer, then externally tie both channel's reference pins together.
7.4.2 LVDS Test Modes
The LVDS test modes present programmable data patterns to the input of the LVDS serializer block. The type of
pattern is selectable through the Test Pattern Control register. Once the LVDS test mode is enabled the patterns
are output indefinitely. Table 4 below shows the available test pattern modes.
TEST PATTERN CONTROL[6:4]
000
001
010
011
100
101
110
111
Table 4. Test Pattern Modes
TEST MODE
Fixed Code
Horizontal Gradient
Vertical Gradient
Lattice Pattern
Strip Pattern
LVDS Test Pattern (Synchronous)
LVDS Test Pattern (Asynchronous)
Reserved
32
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: LM98640QML-SP