LM98640QML-SP Datasheet, PDF (23/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

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LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
Feature Description (continued)
commonly a difference in switched capacitor matching), the processing of identical pixels through the two
different paths may result in a small offset in ADC output data between the two paths. To correct this, a simple
digital offset can be applied in post processing to either the even pixel data or the odd pixel data. To simplify this
action, the LM98640QML will indicate (with the TXFRM signal) whether the pixel traveled the even path or the
odd path. For all "Odd" pixels, the TXFRM signal is high for three TXCLK periods. For "Even" pixels, the TXFRM
signal is high for two TXCLK periods. In Sample and Hold Mode there is only one sampling path, therefore there
is no need to indicate an even or odd pixel. As a result, the TXFRM signal is the same for every pixel in Sample
and Hold mode (i.e. high for three TXCLK periods).
7.3.1.2.2 CDS Mode CLAMP/SAMPLE Adjust
In CDS mode, the LM98640QML utilizes two input networks, alternating between them every pixel, to increase
throughput speeds. Because of this, there are two sets of CLAMP and SAMPLE pulses in the Table 8, one for
even pixels and one for odd. Sample Start and Sample End Registers (0x22,0x23) along with the Clamp Start
and Clamp End Registers (0x20,0x21) control both the even and odd CLAMP and SAMPLE pulses. To adjust the
CLAMP and SAMPLE pulses, first send the CLAMP_ODD and SAMPLE_ODD signals to the DTM pins by writing 10
to bits[4:3] of the Clock Monitor Register (0x09). This will allow the user to observe the CLAMP_ODD and
SAMPLE_ODD pulses on pins DTM0 and DTM1 along with the image sensor output using an oscilloscope. The
CLAMP and SAMPLE pulses will only be shown for every other pixel because of the even odd architecture, but
the positions of the even CLAMP and SAMPLE pulses will be identical to that of the odd CLAMP and SAMPLE.
Then, using the Clamp Start/End and Sample Start/End registers, adjust the positions of the CLAMP and
SAMPLE pulses to align them over the Reference and Video Levels of the input signal. To allow for settling and
to reduce noise, the CLAMP and SAMPLE pulses should be made as wide as possible and placed near the far
edge of their respective input levels.
The following figure shows some examples of input CCD waveforms and placement of the CLAMP and SAMPLE
positions for each. Ideally the CCD output would line up directly with the input clock at the AFE inputs, but due to
trace delays in the system the CCD output is delayed relative to the input clock. In the Delayed CCD waveform
the Sample Start/End Register values are lower than the Clamp Start/End Register Values. In this situation the
sample pulse is not generated until the next clock period, which allows it to be correctly placed in the Video Level
of the input signal. Notice that edge zero of the internal clock does not line up with the rising edge of the input
clock. This is due to internal delays of the clock signals. The amount of delay can be calculated from operating
frequency using the following formula: t_DCLK = 6.0ns + 3/64 * T_INCLK
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