LM98640QML-SP Datasheet, PDF(42/54 Page) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

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LM98640QML-SP Datasheet, PDF (42/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

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LM98640QML-SP

SNAS461D â MAY 2010 â REVISED SEPTEMBER 2015

ADDRESS

(BINARY)

01 0000

01 0001

01 0010

01 0011

01 0101

01 1000

01 1001

01 1010

01 1011

01 1100

Table 7. Register Definitions - GAIN & Offset DAC Configuration

TITLE

CDAC1

BASELINE

(BINARY)

0000 0000

BIT(s)

DESCRIPTION

[7:0] Channel 1 Coarse DAC Register.

[7:1] Not Used.

CDAC1

FDAC1

1111 1111

0000 0000

[0] Bit 8 of Channel 1 Coarse DAC Offset Value.

[7:0] Channel 1 Coarse DAC Offset Value bits 7:0.

[7:0] Channel 1 Fine DAC Register.

[7:1] Not Used.

FDAC1

PGA1

CDAC2

1111 1111

0110 0001

0000 0000

[0] Bit 8 of Channel 1 Fine DAC Offset Value.

[7:0] Channel 1 Fine DAC Offset Value bits 7:0.

[7:0] Channel 1 Programmable Gain Amplifier Value.

[7:0] Channel 2 Coarse DAC Register.

[7:1] Not Used.

CDAC2

FDAC2

1111 1111

0000 0000

[0] Bit 8 of Channel 2 Coarse DAC Offset Value.

[7:0] Channel 2 Coarse DAC Offset Value bits 7:0.

[7:0] Channel 2 Fine DAC Register.

[7:1] Not Used.

FDAC2

PGA2

1111 1111

0110 0001

[0] Bit 8 of Channel 2 Fine DAC Offset Value.

[7:0] Channel 2 Fine DAC Offset Value bits 7:0.

[7:0] Channel 2 Programmable Gain Amplifier Value.

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