LM98640QML-SP Datasheet, PDF (26/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
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Feature Description (continued)
7.3.2.1 Sample and Hold Mode Biasing
Proper DC biasing of the CCD waveform in Sample and Hold mode is critical for realizing optimal operating
conditions. In Sample/Hold Mode, the DC bias point of the input pin is typically set by actuating the input clamp
switch (see Figure 17) during optical black pixels which connects the input pins to the VCLP pin DC voltage. The
signal controlling this switch is CLPIN. CLPIN is an external signal connected on the CLPIN pin.
Actuating the input clamp will force the average value of the CCD waveform to be centered around the VCLP DC
voltage. During Optical Black Pixels, the CCD output has roughly three components. The first component of the
pixel is a “Reset Noise” peak followed by the Reset (or Pedestal) Level voltage, then finally the Black Level
voltage signal. Taking the average of these signal components will result in a final “clamped” DC bias point that
is close to the Black Level signal voltage.
To provide a more precise DC bias point (i.e. a voltage closer to the Black Level voltage), the CLPIN pulse can
be “gated” by the internally generated CLAMP clock. This resulting CLPIN_GATED signal is the logical “AND” of the
CLAMP and CLPIN signals as shown in Figure 18. By using the CLPIN_GATED signal, the higher Reset Noise peak
will not be included in the clamping period and only the Pedestal Level components of the CCD waveform will be
centered around VCLP.
OS_X-
OS_X+
SAMPLE
C_PAR
CLAMP
CPAR
C_S
HOLD
C_S
Figure 19. Sample and Hold Mode Simplified Input Diagram
In Sample and Hold Mode, the impedance of the analog input pins is dominated by the switched capacitance of
the CDS/Sample and Hold amplifier. The amplifier switched capacitance, shown as C_S in Figure 19, and internal
parasitic capacitances can be estimated by a single capacitor switched between the analog input and the VCLP
reference pin for Sample and Hold mode. During each pixel cycle, the modeled capacitor, C_SH, is charged to the
OS_X+ minus OS_X- voltage then discharged. The average input current at the OS_X- pin can be calculated knowing
the input signal amplitude and the frequency of the pixel.
OS_X-
f_PIXEL
C_SH
OS_X+
Figure 20. Equivalent Input Switched Capacitance S/H Mode
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