LM98640QML-SP Datasheet, PDF(38/54 Page) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

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LM98640QML-SP Datasheet, PDF (38/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

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LM98640QML-SP

SNAS461D â MAY 2010 â REVISED SEPTEMBER 2015

www.ti.com

7.6.1 Register Definitions

NOTE: Registers need to be written with baseline values after power-up to place part in a valid state.

ADDRESS

(BINARY)

00 0000

Table 6. Register Definitions - Analog Configuration

TITLE

Main Configuration

BASELINE

(BINARY)

0000 0100

BIT(s)

[7:0] Main Configuration

DESCRIPTION

[7] Not Used

[6] Coarse DAC Enable

0 Disable

1 Enable

[5] Fine DAC Enable

0 Disable

1 Enable

[4] Reserved

[3] CLPIN Gating Enable

0 CLPIN not gated by CLAMP

1 CLPIN gated by CLAMP (=logical "and" of CLPIN and CLAMP)

[2] Gain Mode Select. Selects either a 1x or 2x gain mode in the

CDS/Sample/Hold Block

0 1x Gain in the CDS/Sample/Hold Block

1 2x Gain in the CDS/Sample/Hold Block

[1] Reserved. Set to 0.

[0] CDS / Sample/Hold Mode select.

0 Disabled. Correlated Double Sample Mode disabled.

1 Enabled. Correlated Double Sample Mode enabled.

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