LM98640QML-SP Datasheet, PDF (10/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
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LM98640QML Electrical Characteristics⁽¹⁾⁽²⁾ (continued)
The following specifications apply for VDD33 = 3.3V, VDD18 = 1.8V, C_L = 10pF, and f_INCLK = 40MHz unless otherwise
specified.
PARAMETER
TEST CONDITIONS
NOTES
SUB-
GROUPS
MIN TYP⁽³⁾ MAX UNIT
POWER SUPPLY SPECIFICATIONS (see Power Trimming section for PGA and ADC Power Trimming register settings)
VDD33 Analog Supply Current
Dual Channel
Power optimized for
PGA Gain = 1-4x
Powerdown Control Reg
= 0x00
5 MHz
15 MHz
25 MHz
1, 2, 3
51.5
58
61.3
69
mA
69.6
79
40 MHz
87.6
98
VDD33 Analog Supply Current
Dual Channel
Power optimized for
PGA Gain = 1-8x
Powerdown Control Reg
= 0x00
5 MHz
15 MHz
25 MHz
1, 2, 3
51.5
58
61.3
68
mA
72.9
82
40 MHz
91.3 103
Powerdown Control Reg
IA
VDD33 Analog Supply Current
= 0x15 (CH1 PD) or
= 0x2A (CH2 PD)
Single Channel
5 MHz
Power optimized for
PGA Gain = 1-4x
15 MHz
25 MHz
1, 2, 3
29.5
35
36.1
42
mA
42
47
40 MHz
53.7
60
VDD33 Analog Supply Current
Single Channel
Power optimized for
PGA Gain = 1-8x
Powerdown Control Reg
= 0x15 (CH1 PD) or
= 0x2A (CH2 PD)
5 MHz
15 MHz
25 MHz
1, 2, 3
29.5
35
36.1
42
mA
43.8
50
40 MHz
55.6
64
VDD33 Analog Supply Current
Powerdown
Powerdown Control Reg
= 0x80
1, 2, 3
2.85 3.85 mA
VDD18 Digital Supply Current
LVDS Quad Lane Mode
LVDS Output Mode Reg
= 0x0E
5 MHz
15 MHz
25 MHz
40 MHz
36
39
mA
42
45
ID
5 MHz
VDD18 Digital Supply Current
15 MHz
25 MHz
1, 2, 3
23.5
29
25.5
31
mA
27.5
33
40 MHz
30.5
37
VDD18 Digital Supply Current
Powerdown
Powerdown Control
Reg = 0x80
1, 2, 3
1.2 3.0 mA
PWR
Average Power Dissipation
Power optimized for
PGA Gain = 1-4x
Dual Channel
LVDS Dual Lane Mode
Average Power Dissipation
Power optimized for
PGA Gain = 1-8x
Dual Channel
LVDS Dual Lane Mode
5 MHz
15 MHz
25 MHz
40 MHz
5 MHz
15 MHz
25 MHz
40 MHz
1, 2, 3
1, 2, 3
212 244
250 284
mW
280 320
345 390
212 244
250 284
mW
290 330
356 407
10
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