LM98640QML-SP Datasheet, PDF (16/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
www.ti.com
6.7 AC Timing Specifications
The following specifications apply for VDD33 = 3.3 V, VDD18 = 1.8 V, C_L = 10 pF, and f_INCLK = 15 MHz unless otherwise
specified.
PARAMETER
TEST CONDITIONS
NOTES
SUB-
GROUPS
MIN TYP⁽¹⁾ MAX UNIT
INPUT CLOCK TIMING SPECIFICATIONS
f_INCLK
Input clock frequency
INCLK = ADCCLK
(ADC Rate Clock)
9, 10, 11
5
40 MHz
T_dc
Input clock duty cycle
t_LAT
Pipeline latency
LVDS OUTPUT TIMING SPECIFICATIONS
See ⁽²⁾
9, 10, 11
40/60% 50/50 60/40%
10 T_ADC
t_DOD
t_DSO
Data output delay
Dual lane mode
Odd data setup
f_INCLK = 40MHz
INCLK = ADCCLK
(ADC Rate Clock)
LVDS Output Specifications
Dual lane mode
t_DSE
Even data setup
not tested in production.
Min/Max ensured by design,
characterization and
Quad lane mode
t_QSR
Data to rising clock setup
statistical analysis.
9, 10, 11
9, 10, 11
6.44
0.45 0.69
7.50 ns
ns
9, 10, 11
0.45 0.89
ns
9, 10, 11
0.45 0.63
ns
Quad lane mode
t_QHF
Falling clock to data hold
9, 10, 11
0,45 0.53
ns
SERIAL INTERFACE TIMING SPECIFICATIONS
f_SCLK
Input clock frequency
f_SCLK <= f_INCLK
INCLK = ADCCLK
(ADC Rate Clock)
9, 10, 11
1
20 MHz
SCLK duty cycle
9, 10, 11 40/60 50/50 60/40 ns
t_IH
t_IS
t_SENSC
t_SCSEN
Input hold time
Input setup time
SCLK start time after SEN low
SEN high after last SCLK rising
edge
9, 10, 11
2.5
1
ns
9, 10, 11
2.5
1
ns
9, 10, 11
1.5
1
ns
9, 10, 11
2.5
2
ns
t_SENW
t_OD
t_HZ
SEN pulse width
Output delay time
Data output to high Z
9, 10, 11
9, 10, 11
9, 10, 11
8
6
ns
10.54 11.6 ns
1.2
1.23 ^TSCL
K
(1) Typical figures are at T_A = 25°C, and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
(2) This Parameter is ensured by design and/or characterization and is not tested.
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