LM98640QML-SP Datasheet, PDF (22/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
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Feature Description (continued)
Figure 15 shows some examples of an input waveform and where the SAMPLE pulse should be placed. Ideally
the image sensor output would line up directly with the input clock at the AFE inputs, but due to trace delays in
the system the image sensor output is delayed relative to the input clock. In the delayed image sensor waveform
the Sample Start value is higher than the Sample End value. In this situation the SAMPLE pulse will start in one
clock period and wraps around to the next. This allows the LM98640QML to adjust for the delay in the image
sensor waveform. Notice that edge zero of the internal clock does not line up with the rising edge of the input
clock. This is due to internal delays of the clock signals. The amount of delay can be calculated from operating
frequency using the following formula: t_DCLK = 6.0ns + 3/64 * T_INCLK
INCLK (Pixel Rate)
TINCLK
Internal Clock
(64 selectable
positions)
Internal Clock Delay = 6.0ns + 3/64 * TINCLK
0x00
0x1F
0x3F 0x00
0x1F
Ideal
Pixel output from CCD
SAMPLE
(internal pixel video
level sampling clock)
Sample Start = 0x22
Sample End = 0x3B
Delayed
Pixel output from CCD
SAMPLE
(internal pixel video
level sampling clock)
Sample Start = 0x2F
Sample End = 0x04
Figure 15. S/H Mode CLAMP/SAMPLE Adjust
7.3.1.2 CDS Mode
In CDS mode, both the Reference Level and Video Level are presented to the LM98640QML on the OS_X- pin.
The OS_X+ pin should be bypassed to ground with a 0.1uF capacitor. The CLAMP pulse is then used to sample
the Reference Level and the SAMPLE pulse is used to sample the Video Level. The output code will then be the
Reference Level minus the Video Level, or the difference between the Reference Level and Video Level. A
minimum code represents zero deviation between the Reference and Video Levels and a maximum code
represents a 2V deviation between the Reference and Video Levels with CDS and PGA gains of 1x.
To place the LM98640QML in CDS Mode from power up, first write the baseline configuration to the registers as
shown in Table 5. Then ensure S/H mode is disabled by clearing bit[7] of the Sample & Hold Register (0x06),
then enable CDS mode by setting bit[0] of the Main Configuration Register (0x00). Next the CLAMP and
SAMPLE pulses need to be positioned correctly over the reference and video levels respectively using the
CLAMP/SAMPLE Adjust.
7.3.1.2.1 CDS Mode Bimodal Offset
In CDS mode, the input sampling amplifier has two physical paths through which a particular pixel will be
sampled. These two sampling paths are a requirement in the Correlated Double Sampling architecture. The
sampling of the one pixel will travel the first path (arbritrarily called an even pixel), and the sampling of the next
pixel will travel the second path (called an odd pixel). The sampling will continue in an even/odd/even/odd
fashion for all pixels processed in a particular channel. Due to slight variances in the sampling paths (most
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