LM98640QML-SP Datasheet, PDF (24/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
Feature Description (continued)
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INCLK (Pixel Rate)
Internal Clock
(64 selectable
positions)
Ideal
Pixel output from CCD
CLAMP
(internal pixel reference
level sampling clock)
SAMPLE
(internal pixel video
level sampling clock)
TINCLK
Internal Clock Delay = 6.0ns + 3/64 * TINCLK
0x00
0x1F
0x3F 0x00
Clamp Start = 0x04
Clamp End = 0x18
Sample Start = 0x25
Sample End = 0x3A
0x1F
Delayed
Pixel output from CCD
CLAMP
(internal pixel reference
level sampling clock)
SAMPLE
(internal pixel video
level sampling clock)
Clamp Start = 0x1C
Clamp End = 0x32
Sample Start = 0x3E
Sample End = 0x12
Figure 16. CDS Mode CLAMP/SAMPLE Adjust
7.3.2 Input Bias and Clamping
The inputs to the LM98640QML are typically AC coupled and can be sampled in either Sample and Hold Mode
(S/H Mode) or Correlated Double Sampling Mode (CDS Mode). The circuit of Figure 17 shows the input structure
of the LM98640QML. The DC bias point for the LM98640QML side of the AC coupling capacitor can to be set
using an external DC bias resistor network, by using the CLPIN configuration, or by using the BITCLP
configuration. A typical CCD waveform is shown in Figure 18. Also shown in Figure 18 is an internal signal
“CLAMP” which can be used to “gate” the CLPIN signal so that it only occurs during the “pedestal” portion of the
CCD pixel waveform.
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