LM98640QML-SP Datasheet, PDF (4/54 Pages) Texas Instruments – Dual Channel, 14-Bit, 40 MSPS Analog Front End with LVDS Output

LM98640QML-SP
SNAS461D – MAY 2010 – REVISED SEPTEMBER 2015
www.ti.com
Pin
Name
1 VCOM1
2 VDD33
3 VDD33
4 VSS33
5 VSS33
6 OS1-
7 OS1+
8 VSS33
9 VCLP
10 VSS33
11 OS2+
12 OS2-
13 VSS33
14 VSS33
15 VDD33
16 VDD33
17 VCOM2
18 VREFB2
19 VREFT2
20 VSS33
21 VSS33
22 VDD33
23 VDD33
24 VSS33
25 SDO
26 SDI
27 SCLK
28 SEN
29 NC
30 CLPIN
31 VSS18
32 VDD18
33 DTM1
34 DTM0
35 VDD18
36 VSS18
37 TXFRM+
38 TXFRM-
39 TXOUT3+
40 TXOUT3-
41 TXOUT2+
42 TXOUT2-
43 TXOUT1+
44 TXOUT1-
45 TXOUT0+
I/O⁽¹⁾ Typ
O
A
P
P
P
P
I
A
I
A
P
O
A
P
I
A
I
A
P
P
P
P
O
A
O
A
O
A
P
P
P
P
P
O
D
I
D
I
D
I
D
I
D
P
P
O
D
O
D
P
P
O
D
O
D
O
D
O
D
O
D
O
D
O
D
O
D
O
D
Pin Functions
Res
Description
Common mode of ADC reference. Bypass with 0.1µF capacitor to VSS33.
Analog power supply. Decouple with minimum 0.1µF capacitor to VSS33 plane.
Analog power supply. Decouple with minimum 0.1µF capacitor to VSS33 plane.
Analog supply return.
Analog supply return.
Analog input signal.
Sample/Hold Mode Reference Level. Bypassed with a 0.1µF to ground in CDS mode.
Analog supply return.
Programmable Clamp Voltage output. Normally bypassed with a 0.1µF capacitor to
VSS33.
Analog supply return.
Sample/Hold Mode Reference Level. Bypassed with a 0.1µF to ground in CDS mode.
Analog input signal.
Analog supply return.
Analog supply return.
Analog power supply. Decouple with minimum 0.1µF capacitor to VSS33 plane.
Analog power supply. Decouple with minimum 0.1µF capacitor to VSS33 plane.
Common mode of ADC reference. Bypass with 0.1µF capacitor to ground.
Bottom of ADC reference. Bypass with a 0.1µF capacitor to ground.
Top of ADC reference. Bypass with a 0.1µF capacitor to ground.
Analog supply return.
Analog supply return.
Analog power supply. Decouple with minimum 0.1µF capacitor to VSS33 plane.
Analog power supply. Decouple with minimum 0.1µF capacitor to VSS33 plane.
Analog supply return.
Serial Interface Data Output. (Tri-State when SEN is high)
Serial Interface Data Input. (Tri-State when SEN is high)
PD Serial Interface shift register clock. (Tri-State when SEN is high)
PU Active-low chip enable for the Serial Interface.
No Connection. Can be connected to VSS18.
Input clamp signal.
Digital supply return.
Digital power supply. Decouple with minimum 0.1µF capacitor to VSS18 plane.
Digital Timing Monitor. If not used, can be connected to VDD18 through a 10kΩ resistor.
Digital Timing Monitor. If not used, can be connected to VDD18 through a 10kΩ resistor.
Digital power supply. Decouple with minimum 0.1µF capacitor to VSS18 plane.
Digital supply return.
LVDS Frame+
LVDS Frame-
LVDS Data Out3+
LVDS Data Out3-
LVDS Data Out2+
LVDS Data Out2-
LVDS Data Out1+
LVDS Data Out1-
LVDS Data Out0+
(1) (I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog), (PU=Pull Up with an internal resistor), (PD=Pull Down
with an internal resistor.).
4
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